DA9179.002
19 May, 2005
MAS9179 SAMPLES IN SBDIL 20 PACKAGE
NC 1
VDD 2
QO2 3
QO1 4
QO3 5
NC 6
QI 7
AGC 8
PDN2 9
OUT 10
9179Az
YYWW
XXXXX.X
20 VSS
19 RFI2
18 RFIM
17 RFIP
16 RFI3
15 NC
14 PDN1
13 AON
12 DEC
11 NC
Top Marking Definitions:
YYWW = Year Week
XXXXX.X = Lot Number
z = Sample Version Number
PIN DESCRIPTION
Pin Name
NC
VDD
QO2
QO1
QO3
NC
QI
AGC
PDN2
OUT
NC
DEC
AON
PDN1
NC
RFI3
RFIP
RFIM
RFI2
VSS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Type
P
AO
AO
AO
AI
AO
DI
DO
AO
DI
DI
AI
AI
AI
AI
G
Function
Positive Power Supply
Quartz Filter Output for Crystal 2
Quartz Filter Output for Crystal 1
Quartz Filter Output for Crystal 3
1
Quartz Filter Input for Crystal
AGC Capacitor
Power Down/Frequency Selection Input 2
Receiver Output
Demodulator Capacitor
AGC On Control
Power Down/Frequency Selection Input 1
Receiver Input 3 (for Antenna Capacitor 3)
Positive Receiver Input
Negative Receiver Input
Receiver Input 2 (for Antenna Capacitor 2)
Power Supply Ground
Note
3
2
4
3
5
5
A = Analog, D = Digital, P = Power, G = Ground, I = Input, O = Output, NC = Not Connected
Notes:
1) Pin 6 between QO3 and QI must be connected to VSS to eliminate DIL package leadframe parasitic
capacitances disturbing the crystal filter performance. All other NC (Not Connected) pins are also
recommended to be connected to VSS to minimize noise coupling.
2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced
(modulated)
-
the output is a current source/sink with |I
OUT
| > 5
µA
-
at power down the output is pulled to VSS (pull down switch)
3) PDN1 = VDD and PDN2 = VDD means receiver off
-
Fast start-up is triggered when the receiver is after power down controlled to power up
4) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)
-
Internal pull-up with current < 1
µA
which is switched off at power down
5) Receiver inputs RFIP and RFIM have both 600 kΩ biasing MOSFET-transistors towards ground
8 (9)
MAS [ MICRO ANALOG SYSTEMS ]
