DA7838.002
20 September, 2000
3,1 &21),*85$7,21
PDIP 16
SO16
MAS7838N
TSL 1
TMG 2
OSC 3
TXC 4
CL1 5
CL2 6
XESR 7
VSS 8
Ã
Ã
Ã
`
`
X
Y
Y
Y
Y
Y
X
Y
Ã
Ã
Ã
Ã
Ã
Ã
Ã
&
'
"
'
16 VDD
15 RXC
14 RDI
13 RDO
12 XHST
11 XASY
10 TDO
9 TDI
TSL
TMG
OSC
TXC
CL1
CL2
XESR
VSS
1
2
3
4
5
6
7
8
MAS7838S
16
15
14
13
12
11
10
9
VDD
RXC
RDI
RDO
XHST
XASY
TDO
TDI
Ã
Ã
Ã
`
`
X
Y
Y
Y
Y
Y
X
Y
Ã
Ã
Ã
Ã
Ã
Ã
Ã
&
'
"
'
Top marking: YYWW = Year Week, XXXXX.X = Lot Number,
=ESD Indicator
)XQFWLRQ
3,1 '(6&5,37,21
3LQ QDPH
TSL
TMG
OSC
TXC
3LQ QR
1
2
3
4
,2
I
I
O
I
Timing select. 0 selects asynchronous sampling timing 16 x TXC from pin 2, TMG.
1 selects asynchronous sampling timing 256...8192 x TXC from pin 2, TMG.
Timing. Square wave timing signal 16 x TXC (TSL=0) or 256...8192 x TXC (TSL=1).
Max f=10 MHz.
Oscillator. Output for crystal. If used, the crystal is connected between pins 2 and 3.
Transmitter timing. Synchronous square wave timing for transmitter. The transmitted
data output, TDO is synchronized to the rising edge of TXC. The duty cycle of TXC
has to be 50% +/- 5%.
Character length. The total character length including one start bit, one stop bit and
possible parity bit is selected with the CL1 and CL2 signals.
Extended signalling rate. The tolerance of the synchronous bit rate can be:
XESR = 1 (basic signalling rate) TXC -2.5%...+1.0%
XESR = 0 (extended signalling rate) TXC -2.5%...2.3%
Ground
Transmitter data input. 1 = mark or stop bit, 0 = space, start or break signal
Transmitter data output. The output data is synchronized to the synchronous timing
signal TXC (pin 4). 1 = mark, 0 = space
Asynchronous mode. XASY=0 Asynchronous transmission. XASY=1 Synchronous
transmission. In synchronous transmission the converter is totally bypassed in both
directions: TDI=TDO, RDI=RDO
Higher speed signalling timing. XHST = 1 normal synchronous to asynchronous
conversion (Bell 212; CCITT V.22). XHST = 0 asynchronous to synchronous
conversion with higher speed synchronous timing (TXC, RXC). TXC and RXC timing
must be 1-2% higher than the normal bit rate in order to allow some overspeed in the
asynchronous data. On the receiver side the RX buffer is deleted and the
synchronous data RDI is directly connected to the asynchronous output RDO.
Receiver data output. RDO is the received data converted back to asynchronous
mode.
1 = mark or stop bit, 0 = space, start or break signal
Receiver data input. 1 = mark, 0 = space. The received data must be synchronized to
the receiver timing RXC from the synchronous channel (pin 15).
Receiver timing. Receiver square wave timing from the synchronous channel. The
received data RDI must be synchronized to the rising edge of RXC.
Power supply
CL1
CL2
XESR
5
6
7
I
I
I
VSS
TDI
TDO
XASY
8
9
10
11
G
I
O
I
XHST
12
I
RDO
13
O
RDI
RXC
VDD
14
15
16
I
I
P
2 (9)
MAS [ MICRO ANALOG SYSTEMS ]
