DA7838.002
20 September, 2000
$%62/87( 0$;,080 5$7,1*6
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Supply Voltage
Storage Temperature
6\PERO
VDD
Ts
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0LQ
-0.5
-55
0D[
5.5
+150
(GND = 0V)
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V
o
C
5(&200('(' 23(5$7,21 &21',7,216
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Supply Voltage
Supply Current
Operating Temperature
6\PERO
VDD
IDD
Ta
0
&RQGLWLRQV
0LQ
4.75
7\S
5
4
0D[
5.25
6
+70
8QLW
V
mA
o
C
(/(&75,&$/ &+$5$&7(5,67,&6
u
,QSXWV
(test conditions: VDD = +5V, VSS = 0V, 0
O
C to 70
O
C)
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Input high voltage
Input low voltage
Input leakage current
Input capacitance load
Internal pull-up resistor for
digital inputs
6\PERO
V
IH
V
IL
I
IL
C
I
R
pull-up
&RQGLWLRQV
0LQ
3.5
7\S
0D[
1.1
8QLW
V
V
pA
pF
k
-100
5
VIN = 0.4v
VIN = 2.5v
350
850
u
2XWSXWV
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(test conditions: VDD = +5V, VSS = 0V, 0
O
C to 70
O
C)
6\PERO
V
OL
V
OH
&RQGLWLRQV
IOL = -0.6mA
IOH = 0.4mA
0LQ
4.6
7\S
0D[
0.4
8QLW
V
V
Output low voltage
Output high voltage
u
'DWD 7LPLQJ
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(test conditions: VDD = +5V, VSS = 0V, 0
O
C to 70
O
C)
6\PERO
tR
tF
&RQGLWLRQV
CL = 10pF
CL = 10pF
0LQ
7\S
20
20
0D[
8QLW
ns
ns
Low to high logic transition time
High to low logic transition time
(test conditions: TSL = 1)
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TDO delay time after TXC
RDI set up time before RXC
RDI hold time after RXC
6\PERO
T1
T2
T3
&RQGLWLRQV
0LQ
50
1/4 T
RXC
1/4 T
RXC
7\S
0D[
T
TXC
/16+350
8QLW
ns
ns
ns
(test conditions: TSL = 0, TMG = 16xTXC)
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TDO delay time after TXC
RDI set up time before RXC
RDI hold time after RXC
6\PERO
T1
T2
T3
&RQGLWLRQV
0LQ
50
1/4 T
RXC
1/4 T
RXC
7\S
0D[
1/TMG+350
8QLW
ns
ns
ns
3 (9)
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