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MAS6512_16 参数 Datasheet PDF下载

MAS6512_16图片预览
型号: MAS6512_16
PDF下载: 下载PDF文件 查看货源
内容描述: [Capacitive Sensor Signal Interface IC]
分类和应用:
文件页数/大小: 32 页 / 1768 K
品牌: MAS [ MICRO ANALOG SYSTEMS ]
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DA6512.003  
2 December, 2016  
FUNCTIONAL DESCRIPTION  
In battery operated applications the VDD of the  
MAS6512 can vary along with battery capacity. In  
such case the VDD level monitoring feature can be  
useful to indicate battery level, help choosing  
between different power modes in the system or  
even using measured VDD level for compensating  
VDD dependencies. In the VDD level monitoring  
mode the on-chip regulator has to be disabled.  
example 10-bit addressing, arbitration and clock  
stretching features of the I2C bus specification.  
The XCLR pin can be used to hard reset the device  
including the serial communication. However device  
reset is possible also via serial bus using the reset  
register. Despite of on chip power on reset (POR)  
circuit it is recommended to reset the device  
manually after every power up to guarantee proper  
register settings after any VDD rise conditions.  
Communication with MAS6512 is handled by the  
serial interface compatible with either  
directional 2-wire I2C bus or a 4-wire SPI bus. The  
XSPI pin is for selecting which bus type is used.  
a
bi-  
The EOC pin indicates if a conversion has finished  
and the result is ready to be read from the memory  
via the serial interface. Using the EOC signal is not  
necessary since it is alternatively possible to wait at  
least maximum conversion time period before  
reading out the result.  
Note: The 2-wire I2C bus of MAS6512 supports only  
basic I2C bus communication protocol but not for  
ABSOLUTE MAXIMUM RATINGS  
All Voltages with Respect to Ground  
Parameter  
Symbol  
Conditions  
Min  
Max  
Unit  
Supply Voltage  
VDD  
-0.3  
-0.3  
-100  
5.0  
V
V
Voltage Range for All Pins  
Latchup Current Limit  
VDD + 0.3  
+100  
ILUT  
For all pins, test according to  
JESD78A.  
mA  
Junction Temperature  
Storage Temperature  
TJmax  
TS  
+ 150  
+125  
°C  
°C  
Note 1  
- 55  
Note 1: See EEPROM memory data retention at hot temperature. Storage or bake at hot temperatures will reduce the wafer level trimming  
and calibration data retention time.  
Note: The absolute maximum rating values are stress ratings only. Functional operation of the device at conditions between maximum  
operating conditions and absolute maximum ratings is not implied and EEPROM contents may be corrupted. Exposure to these conditions  
for extended periods may affect device reliability (e.g. hot carrier degradation, oxide breakdown). Applying conditions above absolute  
maximum ratings may be destructive to the devices.  
Note: This is a CMOS device and therefore it should be handled carefully to avoid any damage by static voltages (ESD).  
RECOMMENDED OPERATION CONDITIONS  
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
Capacitance and VDD level  
monitoring modes  
Note 1  
Supply Voltage  
VDD  
1.8  
2.7  
3.6  
V
Temperature mode  
Note 1  
1.9  
2.7  
3.6  
V
Operating Temperature  
TA  
TA  
-40  
+25  
+25  
+85  
+40  
°C  
°C  
EEPROM Write  
Temperature  
Note 2  
+10  
Note 1. In capacitance measurement and VDD level monitoring the regulator must be disabled (TEMPREGEN=0) which allows operation  
down to 1.8V. In temperature measurement the typ 1.8V regulator has to be enabled (TEMPREGEN=1) which limits the minimum supply  
voltage down to 1.9V.  
Note 2: EEPROM write operation is recommended to be done at room temperature  
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