DA6512.003
2 December, 2016
APPLICATION INFORMATION
VDD rise time < 1ms
VDD
VDD
MCU
100n
GND
OSC
VDD
4k7
MISO
4k7
MUX
CLK
OSC
CS
SDA/MOSI
I2C /
SCL/SCLK
XCS
Cs
SPI
CC
CONTROL
VDD
XSPI
EOC
Cr
CR
optional
optional
optional
XCLR
VREG
TEST1
TEST2
VREG
TEST
TEMP
EEPROM
GND
GND
GND
NOTE: It is recommended to use the XCLR reset feature to solve unexpected error state conditions. In case VDD rise time can
exceed 1ms the device has to be kept in a reset during power up by using the XCLR pin. Violating this may risk EEPROM integrity.
If not used the XCLR pin can be left unconnected since it has internal pull up to VDD.
Figure 9. MAS6512 configured for I2C bus communication
Note: MAS6512 has an effective ESD clamp protection structure that can be triggered if the VDD rises too fast.
For this reason it’s recommended to use a supply decoupling capacitor having a value of 100nF or higher to slow
down the VDD rise time.
Note: The voltage regulator output VREG does not require external capacitor as shown in figure 9. However if an
output capacitor is wanted to be used for extra filtering the capacitor value should not be higher than 6.8nF.
Figure 9 presents MAS6512 application circuit using I2C bus and when VDD rise time is guaranteed to be
always below internal POR circuit delay of 1ms. In case the VDD rise time can exceed 1ms see the next page
application information.
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MAS [ MICRO ANALOG SYSTEMS ]
