DA6505.005
11 June 2018
4-WIRE OR 3-WIRESERIAL DATA INTERFACE (SPI BUS)
Figure 9 illustrates 4-wire (WIRE=0) SPI bus read
access communication. The SDO line is at high
impedance state (HZ) until it outputs the MSB data
bit (DO7) at falling edge of the eight SCK clock pulse.
read the additional data bytes are delivered from
following incremented register addresses.
Returning CSB high ends the SPI communication
and sets the SDO pin to high impedance state (HZ).
The auto increment function can be utilized also in
read access. If there are more than one data byte
CSB
SCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SDI
A7=1(R) A6
A5
A4
A3
A2
A1
A0
SDO
HZ
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
HZ
Figure 9. SPI 4-Wire (WIRE=0) Protocol – Read Access (register address MSB bit A7=1)
Figure 10 illustrates 3-wire (WIRE=1) SPI bus read
access communication. The SDI input line turns into
output after falling edge of the eight SCK clock pulse.
The first read data bit is the MSB bit and the last LSB
bit is send to SDI line at the falling edge of the 15th
SCK clock pulse. Master reads the data bits at the
rising edges of the SCK clock pulses.
The auto increment function can be utilized also in
read access and if there are more than one data byte
read the additional data bytes are delivered from
following register addresses.
In 3-wire SPI bus write access communication the
MAS6505 keeps the SDO line in high impedance
state (HZ) during the whole communication.
CSB
SCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SDI
A7(RW) A6
A5
A4
A3
A2
A1
A0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
Figure 10. SPI 3-Wire (WIRE=1) Protocol – Read Access (register address MSB bit A7=1)
33 (44)
MAS [ MICRO ANALOG SYSTEMS ]
