DA6505.005
11 June 2018
2-WIRE SERIAL DATA INTERFACE (I2C BUS)
Conversion Result – Read Sequence
Table 15 presents a general control sequence for a
single register data (Dx) read from register address
(Ax).
Table 15. MAS6505 I2C bus single register (address Ax) data byte (Dx) read sequence
S
AW
A
Ax
A
Sr AR
A
Dx
N
P
Table 16 shows an incremental read sequence for
reading the 24-bit measurement results of both
temperature and pressure. All the six result bytes
can be read in a single read sequence. This is
possible because of MAS6505 auto increment
function and since pressure and temperature result
register addresses are consecutive. The auto
increment function increments register address
automatically to the next register address when
either read or write sequence is continued (not
ended by a Stop bit P) after each data byte. The read
command is ended by the Stop bit P only after all the
six bytes have been read. The first the three
pressure result registers are read in order MSB
(DPM), LSB (DPL) and XLSB (DPX) and this is
followed by three temperature result registers in the
same order MSB (DTM), LSB (DTL) and XLSB
(DTX).
Table 16. MAS6505 I2C bus incremental read sequence for six measurement result bytes
S
AW
A
AP
A
Sr
AR
A
DPM
A
DPL
A
DPX
A
DTM
A
DTL
A
DTX
N
P
4-WIRE OR 3-WIRE SERIAL DATA INTERFACE (SPI BUS)
The 4-wire serial SPI bus type interface comprises of
serial clock input (SCK), serial data input (SDI),
serial data output (SDO) and chip select input (CSB).
In 3-wire mode the SDO pin is not used and the SDI
pin operates as both data input and data output. The
SPI bus wire selection is done by WIRE bit in the
Configuration register (EE/6EHEX). By default the SPI
bus is in the 4-wire mode (WIRE=0). The 3-wire
mode can be selected by setting WIRE=1.
(SCK) during which the data input line (SDI) should
be kept stable. The selection between write or read
access is done by register address MSB bit A7 (see
Table 1 “Register and EEPROM data addresses”). In
write access the bit A7 is cleared (0) and in read
access it is set (1). The following seven address bits
A6…A0 define register address. The address bits
are followed by eight data bits.
The MAS6505 has an auto increment function which
means that if there are more than one data byte
transferred in write/read by continuing the SCK
clocking the additional data bytes are delivered
to/from following incremented register addresses by
incrementing the register address automatically to
the next address. The SPI bus data transfer is ended
by setting the CSB pin high. In write access
communication the MAS6505 keeps the SDO line in
high impedance state (HZ) during the whole
communication.
In the SPI bus the device selection is done by CSB
chip select pin. By setting the CSB pin low also
activates the SPI bus communication. Note that the
CSB pin has internal pull up and to minimize current
consumption it should be set low only during SPI
communication periods.
Bits are transferred always MSB bit first including
address and data bits. See figure 8 for an example
of a 4- wire and 3-wire write access communication.
The data is latched at rising edges of the serial clock
CSB
SCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SDI
A7(RW) A6
A5
A4
A3
A2
A1
A0
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SDO
HZ
Figure 8. SPI 4-Wire (WIRE=0) and 3-Wire (WIRE=1) Protocol– Write Access (register address MSB bit A7=0)
32 (44)
MAS [ MICRO ANALOG SYSTEMS ]
