DA6502.008
29 November 2012
SERIAL DATA INTERFACE (I2C BUS) CONTROL
Serial Interface
MAS6502 has an I2C bus compatible two wire
serial data interface comprising of serial clock
(SCL) and bi-directional serial data (SDA) pins. Both
the SCL & SDA lines, in the I2C bus, are of open-
drain design, thus, external pull-up resistors are
needed.
communication bus and sets internal registers and
counters to value 00HEX. After connecting the supply
voltage to MAS6502, and before starting operating
the device via the serial bus, it is required to reset
the device with the XCLR reset pin or using reset
register (30HEX) if the supply voltage rise time has
been longer than 400 ns. If the supply voltage rise
time is shorter than this making an external reset is
not necessary since the device is automatically
reset by the power on reset (POR) circuitry. It is
however recommended to use the XCLR reset
feature to solve unexpected error state conditions.
The XCLR pin can be left unconnected when not
used. It has internal pull up to VDD. See Electrical
Characteristics for the XCLR Pin Pull Up Current.
The serial data interface is used to configure and
start the A/D conversion and read the measurement
result when the A/D conversion has been finished.
The digital interface includes also end of conversion
(EOC) and master reset (XCLR) pins. The EOC
goes high when the A/D conversion has finished.
The XCLR signal is active low and used to reset the
reset initializes the serial
A/D converter.
Device Address
A
The I2C bus definition allows several I2C bus
devices to be connected to the same bus. The
devices are distinguished from each other by unique
device address codes. MAS6502 device address is
shown in table 7. The LSB bit of the device address
defines whether the bus is configured for Read (1)
or Write (0) operation.
Table 7. MAS6502 device address
A7 A6 A5 A4 A3 A2 A1
W/R
1
1
1
0
1
1
1
0/1
I2C Bus Protocol Definitions
Data transfer is initiated with a Start bit (S) when
SDA is pulled low while SCL stays high. Then, SDA
sets the transferred bit while SCL is low and the
data is sampled (received) when SCL rises. When
the transfer is complete, a Stop bit (P) is sent by
releasing the data line to allow it to be pulled up
while SCL is constantly high.
data bit. Data must be held stable at the SDA pin
when SCL is high. Data at the SDA pin can change
value only when SCL is low.
Each SDA line byte must contain 8-bits when the
most significant bit (MSB) is always first. Each byte
has to be followed by an acknowledge bit (see
further below). The number of bytes transmitted per
transfer is unrestricted.
Figure 3 shows the start (S) and stop (P) bits and a
S
P
1
0
SDA
SCL
Figure 3. I2C bus protocol definitions
Bus communication includes Acknowledge (A) and
not Acknowledge (N) messages. To send an
acknowledge the receiver device pulls the SDA low
for one SCL clock cycle. For not acknowledge (N)
the receiver device leaves the SDA high for one
SCL clock cycle in which case the master can then
generate either a Stop (P) bit to abort the transfer,
or a repeated Start (Sr) bit to start a new transfer.
Abbreviations:
A= Acknowledge by Receiver
N = Not Acknowledge by Receiver
S = Start
P = Stop
= from Master (MCU) to Slave (MAS6502)
= from Slave (MAS6502) to Master (MCU)
Sr = Repeated Start
11 (20)
MAS [ MICRO ANALOG SYSTEMS ]
