DA6181B.003
17 September, 2014
PIN CONFIGURATION & TOP MARKING FOR PLASTIC TSSOP-16 PACKAGE
VSS
RFI2
RFIM
RFIP
VDD
QO2
QO1
QI
AGC
PDN1
AON
DEC
Top Marking Definitions:
z = Version Number
YYWW = Year Week
PDN2
OUT
PIN DESCRIPTION
Pin Name
Pin
Type
Function
Note
VDD
QO2
QO1
1
2
3
4
5
P
Positive Power Supply
AO
AO
NC
AI
Quartz Filter Output for Crystal 2
Quartz Filter Output for Crystal 1
1
QI
Quartz Filter Input for Crystal and External
Compensation Capacitor
AGC Capacitor
AGC
PDN2
OUT
6
AO
DI
7
Power Down/Frequency Selection Input 2
Receiver Output
2
3
8
DO
AO
DI
DEC
9
Demodulator Capacitor
AON
PDN1
10
11
12
13
14
15
16
AGC On Control
4
2
1
5
5
DI
Power Down/Frequency Selection Input 1
NC
AI
RFIP
RFIM
RFI2
VSS
Positive Receiver Input
AI
Negative Receiver Input
AI
Receiver Input 2 (for Antenna Capacitor 2)
Power Supply Ground
G
A = Analog, D = Digital, P = Power, G = Ground, I = Input, O = Output, NC = Not Connected
Notes:
1) Pin 4 between QOM and QI must be connected to IC’s filtered VDD (pin 1) to eliminate TSSOP package
lead frame parasitic capacitances disturbing the crystal filter performance and minimizing noise coupling. All
other NC (Not Connected) type pins are recommended to be connected to VSS.
2) PDN1 = VDD and PDN2 = VDD means receiver off
Fast start-up is triggered when the receiver is after power down controlled to power on
-
3) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced
(modulated)
-
The output is a current source/sink with |IOUT| > 5 µA
At power down the output is pulled to VSS (pull down switch)
-
4) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (normal operation)
-
Unused AON pad can be left unconnected due to internal pull-up with current < 1 µA. Pull up current is
switched off at power down.
5) Receiver inputs RFIP and RFIM have both 1.4 MΩ biasing resistors towards VDD
10 (14)
MAS [ MICRO ANALOG SYSTEMS ]
