MCP795WXX/MCP795BXX
2.0
PIN DESCRIPTION
The descriptions of the pins are listed in Table 2-1.
2.5
Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the MCP795XXX. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
FIGURE 2-1: DEVICE PINOUTS
SOIC/TSSOP
X1
1
14
Vcc
X2
2
3
4
13
12
11
CLKOUT/BOOT
EVHS
2.6
Interrupt Output (IRQ)
V
BAT
The IRQ pin is shared with the onboard event detect
and the Alarms. This pin requires an external pull-up to
VCC or VBAT. The onboard N-Channel will pull the pin
low during an event detection or an alarm. The pin
remains low until such time that the interrupt flag in the
register is cleared by software. This pin has a maxi-
mum sink current of 10mA.
WDO
IRQ
CS
EVLS
5
10
SCK
6
7
9
8
SI
VSS
SO
2.7
X1, X2
2.1
Chip Select (CS)
The X1 and X2 pins connect to the onboard oscillator
block. X1 is the input to the module and X2 is the out-
put of the module. The device can be run from an
external CMOS signal by feeding into the X1 pin. If
driving X1 the X2 pin should be a No Connect.
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already initi-
ated or in progress will be completed, regardless of the
CS input signal. If CS is brought high during a program
cycle, the device will go in Standby mode as soon as
the programming cycle is complete. When the device is
deselected, SO goes into the high-impedance state,
allowing multiple parts to share the same SPI bus. A
low-to-high transition on CS after a valid write
sequence initiates an internal write cycle. After power-
up, a low level on CS is required prior to any sequence
being initiated.
2.8
VBAT
The VBAT pin is a secondary supply input to maintain
the Clock and SRAM contents when VCC is removed.
2.9
CLKOUT/BOOT
The CLKOUT is a push-pull output that can be used to
generate a squarewave or is used for the boot-up clock
output at power-up. Please refer to Section 9.1.2,
Clockout Function for more details.
2.2
Serial Output (SO)
2.10 EVHS and EVLS
The SO pin is used to transfer data out of the
MCP795XXX. During a read cycle, data is shifted out
on this pin after the falling edge of the serial clock.
The EVHS and EVLS are inputs for the High and Low
Speed Event Detection circuit.
TABLE 2-1:
Pin Name
PIN DESCRIPTIONS
Pin Function
2.3
Watchdog Output (WDO)
VSS
X1
Ground
This pin is a hardware open drain from the internal
watchdog circuit. This pin requires an external pull-up
to VCC. When a watchdog overflow occurs the onboard
N-Channel will pulse this pin low. The pulse duration is
user selectable (Address 0x0A:4). This pin has a max-
imum sink current of 10mA.
Xtal Input, External Oscillator Input
Xtal Output
X2
VBAT
VCC
SI
Battery Backup Input (3V Typ)
+1.8V to +5.5V Power Supply
Serial Input
WDO
SCK
Watchdog Output
2.4
Serial Input (SI)
Serial Clock
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
CLKOUT/
BOOT
Clock Out (Boot Clock on
MCP795BXX)
CS
Chip Select
IRQ
Interrupt Ouput
EVHS
EVLS
SO
High-Speed Event Detect Input
Low-Speed Event Detect Input
Serial Output
DS22280A-page 6
Preliminary
2011 Microchip Technology Inc.
MAS [ MICRO ANALOG SYSTEMS ]
