MCP795WXX/MCP795BXX
REGISTER 5-9:
CONTROL REG 0X08
RW
RW
SQWE
bit 6
RW
RW
RW
RW
RW
RW
OUT
ALM1
ALM0
EXTOSC
RS2
RS1
RS0
bit 7
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7
bit 6
Bit 7 is the OUT bit, this sets the logic level on the CLKOUT when not using this as a square wave output.
Bit 6 is the SQWE bit, setting this bit enables the divided output from the crystal oscillator.
bit 5:4 ALM1 Bits <5:4> determine which alarms are active.
- 00– No Alarms are active
- 01– Alarm 0 is active
- 10– Alarm 1 is active
- 11– Both Alarms are active
bit 3
Bit 3 is the EXTOSC enable bit. Setting this bit will allow an external 32.768 kHz signal to drive the RTCC
registers, eliminating the need for an external crystal.
bit 2:0 RS2 Bits <2:0> set the internal divider for the 32.768 kHz oscillator to be driven to the CLKOUT. The fol-
lowing frequencies are available. The output is responsive to the Calibration register.
- 000– 1 Hz
- 001– 4.096 kHz
- 010– 8.192 kHz
- 011– 32.768 kHz
- 1XXenables the Cal Output function. Cal output appears on CLKOUT if SQWE is set (1 Hz nominal).
Note:
When RS2 is set to enable the Cal Output function, the RTCC counters will continue to increment.
REGISTER 5-10: CALIBRATION 0X09
RW
CALIBRATION
bit 7
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7-0 Calibration Value
Note:
This is an 8-bit register that is used to add or subtract clocks from the RTCC counter every minute. The
CALSGN (0x03:7) is the sign bit and indicates if the count should be added or subtracted. The 8 bits in
the Calibration register, with each bit adding or subtracting two clocks, gives the user the ability to add or
subtract up to 510 clocks per minute.
2011 Microchip Technology Inc.
Preliminary
DS22280A-page 15
MAS [ MICRO ANALOG SYSTEMS ]
