MCP795WXX/MCP795BXX
REGISTER 5-12: EVENT DETECT 0X0B
RW
RW
RW
RW
RW
RW
RW
RW
EVHIF
EVLIF
EVEN1
EVEN0
EVWDT
EVLDB
EVHS1
EVHS0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7
bit 6
When the configured number of high speed events has occurred the IRQ pin is asserted and the EVHIF
bit is set in hardware. The clear the IRQ pin and reset the EVHIF bit must be cleared in software.
When an event occurs on the low-speed pin this IRQ pin is asserted and the EVLIF bit is set. This bit must
be cleared by software to reset the module and clear the IRQ pin.
bit 5:4 <1:0> These two bits determine what combination of the high and low-speed modules are enabled.
- 00– Both modules are Off
- 01– Low-speed module enabled, high speed disabled
- 10– Low-speed module disabled, high speed enabled
- 11– Both modules are enabled
bit 3
bit 2
Setting this bit overrides any setting for the High-Speed Event Detection and allows the EVHS pin to clear
the Watchdog Timer. This is edge triggered. Either and H-L or L-H transition will clear the WDT.
This is the Low-Speed Event Debounce setting. Depending on the state of this bit the low-speed pin will
have to remain at the same state for the following periods to be considered valid.
- 0– 31.25 ms
- 1– 500 ms
bit 1:0 EVHS <1:0> These bits determine how many high-speed events must occur before the EVHIF bit is set.
All of these events must occur within 250 ms (based on the uncalibrated 32.768 kHz clock).
- 00– 1st Event
- 01– 4th Event
- 10– 16th Event
- 11– 32nd Event
Note:
Please see Section 9.1.4, Event Detection for more information.
2011 Microchip Technology Inc.
Preliminary
DS22280A-page 17
MAS [ MICRO ANALOG SYSTEMS ]
