JTAG Interface
8
JTAG Interface
The MV78200 JTAG interface is used for chip boundary scan as well as for CPU cores debugger.
TAP controllers implementation is described in the diagram below.
Figure 5: MV78200 TAP Controller
J_TDI
J_TCLK
CPU0 TAP Controller
CPU0 TDO
J_TRST
J_TM S_CPU0
J_TDO
CPU1 TAP Controller
CPU1 TDO
CPU1 enable
reset strap
J_TM S_CPU1
M V78200
TAP Controller
J_TM S_CORE
Boundary Scan TDO
The MV78200 supports the following test modes:
Boundary scan: In this mode, keep J_TMS_CPU high; this will reset the CPUs TAP controllers
and mux the boundary scan TDO signal on the J_TDO pin.
CPU debugger: In this mode, keep J_TMS_CORE high; this will reset the MV78200 TAP
controller and mux the CPU TDO signal on the J_TDO pin.
The two CPU core TAP controllers are chained (CPU0_TDO is connected to CPU1_TDI;
CPU1_TDO is driven on J_TDO pin). In case the chip is configured at reset to single CPU
(DevAD[20] sampled low), the two CPUs TAP controllers are not chained, and CPU0_TDO is
connected to J_TDO pin.
Copyright © 2008 Marvell
December 6, 2008, Preliminary
MV-S104671-U0 Rev. C
Page 63
Document Classification: Proprietary Information
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
