Product Overview
SATA II Host controller
Two XOR DMAs
• Two SATA 2.0 ports
• Useful for RAID application
• Enhanced-DMA [EDMA] for the SATA ports
• Automatic command execution without host
intervention
• Supports XOR operation on up to eight source
blocks
• Supports also iSCSI CRC-32 calculation
• Command queuing support, for up to 128
outstanding commands
• Separate SATA request/response queues
• 64-bit addressing support for descriptors and data
buffers in system memory
• Read ahead
• Advanced interrupt coalescing
• Target mode operation—Two Marvell® devices can
be attached through the SATA ports, enabling data
communication between the MV78200 and another
Marvell SATA device
Interrupt controller
Maskable interrupts to CPU core
(and PCI Express in the case of PCI Express
Endpoint)
Eight General Purpose 32-bit Timer/Counters
SPI port
• General purpose SPI interface
• Also support boot from SPI ROM
Two TWSI interfaces
General purpose TWSI master/slave
24 Multi-Purpose pins dedicated for peripheral
functions and General Purpose I/O
• Each pin can be configured independently
• GPIO inputs can be used to register interrupts from
external devices, and to generate maskable
interrupts
• Advanced drive diagnostics via the ATA SMART
command
Cryptographic engine
• Hardware implementation on encryption and
authentication engines to boost packet processing
speed
• Dedicated DMA to feed the hardware engines with
data from the internal SRAM memory or from the
DDR memory
• Implements AES, DES, and 3DES encryption
algorithms
• Implements SHA1 and MD5 authentication
algorithms
Clock Generation
• Supports internal generation of CPU core clock,
DRAM clock, core clock, GbE clock, USB clock,
and SATA clock from a single 25 MHz reference
clock
• Also supports spread spectrum reference clock
Power Down support
• Supports CPU Wait for Interrupt mode (shut down
CPU core clock)
• Selectable gating of clock trees of different
interfaces
• Supports DRAM self-refresh
• Supports PCI-Express, USB, and SATA PHYs shut
down
Four UART interfaces
• 16550 UART compatible
• Each port has two pins for transmit and receive
operations, and two pins for modem control
functions
• One channel also supports DMA
Time Division Multiplexing (TDM) Interface
• Generic interface to standard SLIC/Codec devices
• Compatible with standard PCM highway formats
• TDM protocol support for two channels, up to 128
time slots
27 x 27 mm FCBGA package, 1mm ball pitch
• SPI interface for codec registers read/write access
• Integrated DMA to transfer voice data to/from
memory buffer
Four Channel Independent DMA controller
• Chaining via linked-lists of descriptors
• Moves data from any interface to any interface
• DMA trigger by software or external hardware
• Supports increment or hold on both Source and
Destination Address
Copyright © 2008 Marvell
MV-S104671-U0 Rev. C
Page 5
December 6, 2008, Preliminary
Document Classification: Proprietary Information
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
