Pin Multiplexing
MPP Multiplexing
Empty fields in Table 26 indicate non-functional settings.
Note
Table 26: MPP Function Summary
MPP
Pin
0x0
0x1
0x2
0x3
0x4
0x5
0x6
MPP[0]
MPP[1]
MPP[2]
MPP[3]
MPP[4]
MPP[5]
MPP[6]
MPP[7]
MPP[8]
MPP[9]
GPIO[0]
(in/out)
GE0_COL
(in)
GE1_TXCLK
OUT (out)
GPIO[1]
(in/out)
GE0_RXERR GE1_TXCTL
(in)
(out)
GPIO[2]
(in/out)
GE0_CRS
(in)
GE1_RXCTL
(in)
GPIO[3]
(in/out)
GE0_TXERR
(out)
GE1_RXCLK
(in)
GPIO[4]
(in/out)
GE0_TXD[4]
(out)
GE1_TXD[0]
(out)
GPIO[5]
(in/out)
GE0_TXD[5]
(out)
GE1_TXD[1]
(out)
GPIO[6]
(in/out)
GE0_TXD[6]
(out)
GE1_TXD[2]
(out)
GPIO[7]
(in/out)
GE0_TXD[7]
(out)
GE1_TXD[3]
(out)
GPIO[8]
(in/out)
GE0_RXD[4]
(in)
GE1_RXD[0]
(in)
GPIO[9]
(in/out)
GE0_RXD[5]
(in)
GE1_RXD[1]
(in)
MPP[10] GPIO[10]
(in/out)
GE0_RXD[6]
(in)
GE1_RXD[2]
(in)
MPP[11]
GPIO[11]
(in/out)
GE0_RXD[7]
(in)
GE1_RXD[3]
(in)
MPP[12] GPIO[12]
(in/out)
GE2_TXCLK
OUT (out)
M_BB (in)
UA0_CTSn
(in)
NAND Flash
REn[0]
(out)
TDM0_
SCSn
(out)
MPP[13] GPIO[13]
(in/out)
GE2_TXCTL
(out)
SYSRST_
OUTn (out)
UA0_RTSn
(out)
NAND Flash
WEn[0]
(out)
TDM_
SCLK
(out)
Copyright © 2008 Marvell
MV-S104671-U0 Rev. C
Page 49
December 6, 2008, Preliminary
Document Classification: Proprietary Information
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
