MV78200
Hardware Specifications
2.2.13
MPP Interface Pin Assignment
Table 16: MPP Interface Pin Assignments
Pin Name
I/O
Pin
Type
Power
Rails
Description
MPP[11:0]
t/s
CMOS
VDDO_D
Multi Purpose Pin
I/O
Various functionalities
NOTE: These pins have internal pullup resistors.
MPP[23:12]
t/s
CMOS
VDDO_C
Multi Purpose Pin
I/O
Various functionalities
NOTE: These pins have internal pullup resistors.
2.2.14
JTAG Interface Pin Assignment
Table 17: JTAG Pin Assignments
Pin Name
I/O
Pin
Type
Power
Rails
Description
JT_CLK
I
CMOS
CMOS
CMOS
VDDO_A
VDDO_A
VDDO_A
JTAG Clock
Clock input for the JTAG controller.
NOTE: This pin is internally pulled down to 0.
JT_RSTn
I
I
JTAG Reset
When asserted, resets the JTAG controller.
NOTE: This pin is internally pulled down to 0.
1
JT_TMS_CPU0
JT_TMS_CPU1
CPU0/1 JTAG Mode Select
Controls CPU0 JTAG controller state.
Sampled with the rising edge of JT_CLK.
NOTE: This pin is internally pulled up to 1.
JT_TMS_CORE
I
CMOS
VDDO_A
Core JTAG Mode Select
Controls the Core JTAG controller state.
Sampled with the rising edge of JT_CLK.
NOTE: This pin is internally pulled up to 1.
JT_TDO
JT_TDI
O
I
CMOS
CMOS
VDDO_A
VDDO_A
JTAG Data Out
Driven on the falling edge of JT_CLK.
JTAG Data In
JTAG serial data input. Sampled with the JT_CLK rising edge.
NOTE: This pin is internally pulled up to 1.
1. If this pull-down conflicts with other devices, the JTAG tool must not use this signal. This signal is not mandatory for the
JTAG interface, since the TAP (Test Access Port) can be reset by driving the JT_TMS signal HIGH for 5 JT_CLK cycles.
If JT_RSTn is not used it should be connected to reset signal. Otherwise the internal pull down will keep the TAP
controller in reset.
MV-S104671-U0 Rev. C
Page 40
Copyright © 2008 Marvell
Document Classification: Proprietary Information
December 6, 2008, Preliminary
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
