MV78200
Hardware Specifications
Figure 26: SPI (Master Mode) Normal Input AC Timing Diagram......................................................................96
Figure 27: SPI (Master Mode) Opposite Output AC Timing Diagram ................................................................97
Figure 28: SPI (Master Mode) Opposite Input AC Timing Diagram...................................................................97
Figure 29: TWSI Test Circuit..............................................................................................................................99
Figure 30: TWSI Output Delay AC Timing Diagram...........................................................................................99
Figure 31: TWSI Input AC Timing Diagram .....................................................................................................100
Figure 32: Device Bus Interface Test Circuit ...................................................................................................102
Figure 33: Device Bus Interface Output Delay AC Timing Diagram ................................................................102
Figure 34: Device Bus Interface Input AC Timing Diagram .............................................................................103
Figure 35: JTAG Interface Test Circuit ............................................................................................................104
Figure 36: JTAG Interface Output Delay AC Timing Diagram .........................................................................105
Figure 37: JTAG Interface Input AC Timing Diagram ......................................................................................105
Figure 38: TDM Interface Test Circuit..............................................................................................................106
Figure 39: TDM Interface Output Delay AC Timing Diagram...........................................................................107
Figure 40: TDM Interface Input Delay AC Timing Diagram..............................................................................107
Figure 41: PCI Express Interface Test Circuit..................................................................................................111
10 Thermal Data (Preliminary)........................................................................................................... 120
11 Package Mechanical Dimensions ................................................................................................ 121
Figure 45: 655 Pin FCBGA Package and Dimensions ....................................................................................121
12 Part Order Numbering/Package Marking..................................................................................... 122
Figure 46: Sample Part Number ......................................................................................................................122
Figure 47: MV78200 Commercial Package Marking and Pin 1 Location.........................................................123
13 Revision History ............................................................................................................................ 124
MV-S104671-U0 Rev. C
Page 12
Copyright © 2008 Marvell
Document Classification: Proprietary Information
December 6, 2008, Preliminary
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
