Clocking
PLLs and Clock Pins
Table 24: CPU1 Frequencies for HCLK = 333 MHz
CPU0
500
CPU1
500, 667, 1000
500, 667, 1000
833
667
833
1000
500, 667, 1000
Table 25: CPU1 Frequencies for HCLK = 400 MHz
CPU0
400
CPU1
400, 600, 800
400, 600, 800
400, 600, 800
1000
600
800
1000
5.2
PLLs and Clock Pins
The MV78200 has the following on-chip PLLs:
PCLK PLL—Generates PCLK/1 (Sheeva™ core clocks) and HCLK (Sheeva™ bus and SDRAM
I/F clock)
TCLK PLL—Generates the internal core frequency
GE_CLK125 PLL—Generates 125 MHz reference clock for the GbE MAC
PCI Express PHY PLL
USB PHY PLL
SATA PHY PLL
The different MV78200 PLLs require dedicated quiet power supplies (AVDD/AVSS).
See the MV76100, MV78100, and MV78200 Design Guide for a detailed description of
these power supplies and required power filtering.
Note
Copyright © 2008 Marvell
December 6, 2008, Preliminary
MV-S104671-U0 Rev. C
Page 45
Document Classification: Proprietary Information
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
