欢迎访问ic37.com |
会员登录 免费注册
发布采购

MV78200-A0-BHO1C100 参数 Datasheet PDF下载

MV78200-A0-BHO1C100图片预览
型号: MV78200-A0-BHO1C100
PDF下载: 下载PDF文件 查看货源
内容描述: 发现™系列的创新CPU系列硬件规格 [Discovery™ Innovation Series CPU Family Hardware Specifications]
分类和应用:
文件页数/大小: 128 页 / 1541 K
品牌: MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
 浏览型号MV78200-A0-BHO1C100的Datasheet PDF文件第17页浏览型号MV78200-A0-BHO1C100的Datasheet PDF文件第18页浏览型号MV78200-A0-BHO1C100的Datasheet PDF文件第19页浏览型号MV78200-A0-BHO1C100的Datasheet PDF文件第20页浏览型号MV78200-A0-BHO1C100的Datasheet PDF文件第22页浏览型号MV78200-A0-BHO1C100的Datasheet PDF文件第23页浏览型号MV78200-A0-BHO1C100的Datasheet PDF文件第24页浏览型号MV78200-A0-BHO1C100的Datasheet PDF文件第25页  
Pin Information  
Pin Descriptions  
2.2.1  
Power Supply Pins  
Table 3 provides the voltage levels for the various interface pins. These also include the analog  
power supplies for the PLLs or PHYS.  
Table 3: Power Supply Pins  
Pin Name  
Pin Type  
Description  
VDD_CPU0  
VDD_CPU1  
Power  
1.1V CPU voltage  
VDD  
Power  
Power  
1.0V core voltage  
VDD_GE  
1.8V or 3.3V I/O supply voltage for the Ethernet interface (for the exact reset  
configuration, refer to Section 7.4, Pins Sample Configuration)  
VDD_M  
Power  
Power  
Power  
1.8V I/O supply voltage for the DRAM interface  
VDDO_A  
VDDO_B  
3.3V I/O supply voltage for the TWSI1, SPI, JTAG interfaces  
1.8V or 3.3V I/O supply voltage for Device Bus[31:16], TWSI0 (for the exact  
reset configuration, refer to Section 7.4, Pins Sample Configuration)  
VDDO_C  
Power  
1.8V or 3.3V I/O supply voltage for the Device Bus[15:0], Device Bus  
controls, MPP[23:12], UART, and system signals:  
REF_CLK_SSC  
REF_CLK_PT  
SYSRSTn  
TCLK_OUT  
TCLK_IN  
(For the exact reset configuration, refer to Section 7.4, Pins Sample  
Configuration.)  
VDDO_D  
Power  
1.8V or 3.3V I/O supply voltage for MPP[11:0] (for the exact reset  
configuration, refer to Section 7.4, Pins Sample Configuration)  
VSS  
GND  
PLL_AVDD  
Power  
PCLK PLL quiet power supply 1.8V  
NOTE: Implement the PLL filter as described in the MV76100, MV78100,  
and MV78200 Design Guide.  
PLL_AVSS  
IREF_AVDD  
M_VREF  
GND  
PCLK PLL quiet VSS  
NOTE: Implement the PLL filter as described in the MV76100, MV78100,  
and MV78200 Design Guide.  
Power  
Power  
SATA and USB PHYs current source voltage filtered 1.8V  
NOTE: Implement the PLL filter as described in the MV76100, MV78100,  
and MV78200 Design Guide.  
SSTL Reference Voltage  
Reference voltage for SSTL interface, typically VDD_M/2.  
Note: See the MV76100, MV78100, and MV78200 Design Guide for the  
VREF recommended topology.  
PEX0_AVDD  
PEX1_AVDD  
Power  
PCI Express PHY quiet power supply 1.8V.  
NOTE: See the MV76100, MV78100, and MV78200 Design Guide for  
power supply filtering recommendations.  
Copyright © 2008 Marvell  
MV-S104671-U0 Rev. C  
December 6, 2008, Preliminary  
Document Classification: Proprietary Information  
Page 21