MV78100
Discovery™ Innovation Series CPU Family
Hardware Specifications
PRODUCT OVERVIEW
Building upon the Marvell
®
high-performance Sheeva
™
CPU core, the MV78100 is part of the Discovery
™
Innovation series CPU family.
The MV78100 is optimally designed for a broad range of
applications ranging from sophisticated routers,
switches, and wireless-base stations to high-volume
storage and laser printer applications.
The MV78100 incorporates a fully ARMv5TE-compliant
dual-issue CPU core with a double-precision, IEEE
compliant Floating-point Unit (FPU), and 512 KB of
L2 cache.
Its innovative crossbar architecture, advanced
communications peripherals, and performance-tuned
interfaces, make it a perfect, high-performance solution
for embedded applications such as:
•
Integrated Storage Accelerator engine (two XOR
DMA or iSCSI CRC engines)
•
Timers
•
Interrupt controller
Sheeva
™
Dual-Issue CPU with FPU support
•
Up to 1.2 GHz
•
Super-scalar, dual-issue CPU
•
Single-precision and double-precision FPU support
•
32-bit and 16-bit RISC architecture
•
Compliant with v5TE architecture, published in the
ARM Architect Reference Manual,
Second Edition
•
Supports 32-bit instruction set for performance and
flexibility
•
Supports 16-bit Thumb instruction set for code
density
•
Supports DSP instructions to boost performance
for signal processing applications
•
Includes MMU to support virtual memory features
•
MPU can be used instead of MMU
•
32-KB I-Cache and 32-KB D-Cache, parity
protected
•
512-KB unified L2 cache, ECC protected
•
64-bit internal data bus
•
Variable pipeline stages—six to nine stages
•
Out-of-order execution for increased performance
•
In-order retire via Reordering Buffer (ROB)
•
Branch Prediction Unit
•
Supports JTAG/ARM-compatible ICE
•
Supports both Big and Little Endian modes
DDR2 SDRAM controller
•
40/72-bit interface (32/64-bit data + 8-bit ECC)
•
Up to 400 MHz clock frequency (DDR2–800 MHz
data rate)
•
DDR SDRAM with a clock ratio of 1:N and 2:N
(up to 1:5) between the DDR SDRAM and the
Sheeva
™
core, respectively
•
SSTL 1.8V I/Os
•
Auto-calibration of I/Os output impedance
•
Supports four DRAM banks
•
Supports all DDR devices, densities up to 2 Gb
•
Up to 4 GB address space
MV-S104552-U0 Rev. D
•
•
•
•
•
•
Printers
Core and edge routers
Cellular base stations
Ethernet switch management
Storage arrays
Network Attached Storage (NAS) devices
The MV78100 Includes
•
High-performance Sheeva
™
dual-issue CPU with
IEEE compliant FPU support
•
512 KB L2 cache
•
High bandwidth DDR II memory interface (32/64-bit
DDR2–800 MHz data rate with an 8-bit ECC
option)
•
8/16/32-bit device bus with up to five chip selects,
and with NAND and NOR Flash support
•
Two x4 wide PCI Express ports with integrated
PHY; each one can also act as four x1 ports
•
Two Gigabit Ethernet MAC controllers
•
Three USB 2.0 ports with integrated PHYs
•
Two SATA 2.0 ports with integrated 3 Gbps SATA II
PHY
•
Security Cryptographic engine
•
Four 16550 compatible UARTs
•
Two channels SLIC/Codec TDM interface
•
Four IDMA engines
Copyright © 2008 Marvell
December 6, 2008, Preliminary
Document Classification: Proprietary Information
Page 3
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