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MV78100-A0-BHO-C100 参数 Datasheet PDF下载

MV78100-A0-BHO-C100图片预览
型号: MV78100-A0-BHO-C100
PDF下载: 下载PDF文件 查看货源
内容描述: 发现™系列的创新CPU系列硬件规格 [Discovery™ Innovation Series CPU Family Hardware Specifications]
分类和应用:
文件页数/大小: 124 页 / 1524 K
品牌: MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
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List of Tables  
Table 27: General 3.3V Interface (CMOS) DC Electrical Specifications...........................................................66  
Table 28: General 1.8V Interface (CMOS) DC Electrical Specifications...........................................................67  
Table 29: SDRAM DDR2 Interface DC Electrical Specifications ......................................................................68  
Table 30: TWSI Interface 3.3V DC Electrical Specifications.............................................................................69  
Table 31: Reference Clock and Reset AC Timing Specifications.....................................................................70  
Table 32: RGMII AC Timing Table....................................................................................................................73  
Table 33: MII AC Timing Table........................................................................................................................75  
Table 34: GMII AC Timing Table ......................................................................................................................77  
Table 35: SMI Master Mode AC Timing Table..................................................................................................79  
Table 36: SDRAM DDR2 400 MHz Interface AC Timing Table........................................................................81  
Table 37: SDRAM DDR2 400 MHz Interface Address and Control Timing Table ............................................82  
Table 38: SDRAM DDR2 400 MHz Clock Specifications..................................................................................83  
Table 39: SDRAM DDR2 333 MHz Interface AC Timing Table........................................................................84  
Table 40: SDRAM DDR2 333 MHz Interface Address and Control Timing Table ............................................85  
Table 41: SDRAM DDR2 333 MHz Clock Specifications..................................................................................86  
Table 42: SDRAM DDR2 266 MHz Interface AC Timing Table........................................................................87  
Table 43: SDRAM DDR2 200 MHz Interface AC Timing Table........................................................................88  
Table 44: SPI (Master Mode) AC Timing Table................................................................................................91  
Table 45: TWSI Master AC Timing Table.........................................................................................................94  
Table 46: TWSI Slave AC Timing Table...........................................................................................................94  
Table 47: Device Bus Interface AC Timing Table (when using TCLK_OUT as the reference clock) ...............97  
Table 48: Device Bus Interface AC Timing Table (when using TCLK_IN as the reference clock) ...................97  
Table 49: JTAG Interface 30 MHz AC Timing Table ......................................................................................100  
Table 50: TDM Interface AC Timing Table .....................................................................................................102  
Table 51: PCI Express Interface Differential Reference Clock Characteristics ..............................................104  
Table 52: PCI Express Interface Spread Spectrum Requirements.................................................................105  
Table 53: PCI Express Interface Driver and Receiver Characteristics ...........................................................106  
Table 54: SATA I Interface Gen1i Mode Driver and Receiver Characteristicss..............................................108  
Table 55: SATA I Interface Gen1m Mode Driver and Receiver Characteristics .............................................109  
Table 56: SATA II Interface Gen2i Mode Driver and Receiver Characteristics ..............................................110  
Table 57: SATA II Interface Gen2m Mode Driver and Receiver Characteristics ............................................111  
Table 58: USB Low Speed Driver and Receiver Characteristics....................................................................112  
Table 59: USB Full Speed Driver and Receiver Characteristics.....................................................................113  
Table 60: USB High Speed Driver and Receiver Characteristics ...................................................................114  
10 Thermal Data (Preliminary)............................................................................................................116  
Table 61: Thermal Data for the MV78100 in FCBGA Package ......................................................................116  
11 Package Mechanical Dimensions .................................................................................................117  
12 Part Order Numbering/Package Marking......................................................................................118  
Table 62: MV78100 Part Order Options .........................................................................................................118  
13 Revision History .............................................................................................................................120  
Table 63: Revision History..............................................................................................................................120  
Copyright © 2008 Marvell  
MV-S104552-U0 Rev. D  
Page 9  
December 6, 2008, Preliminary  
Document Classification: Proprietary Information