MV78100
Hardware Specifications
•
Supports all DIMMs configurations (registered and
•
•
•
•
un-buffered, x8 or x16 DRAM devices)
Supports 2T mode to enable high-frequency
operation, even under heavy load configuration
Supports DRAM bank interleaving
Supports up to 32 open pages
Supports up to 128-byte burst per single memory
access
PCI Express Target specific features
•
Supports reception of up to four read requests
•
Maximum read request of up to 4 KB
•
Maximum write request of up to 128 bytes
•
Supports PCI Express access to all of the device’s
internal registers
Two Gigabit Ethernet MACs
•
Support 10/100/1000 Mbps
•
Full wire speed receive and transmit of short
packets
•
GMII/MII interface when using a single port
•
RGMII interface when using dual ports
•
Priority queueing on receive based on DA,
VLAN-Tag, IP-TOS
•
Also supports queuing based on Marvell DSA Tag
•
Layer2/3/4 frame encapsulation detection
•
Supports long frames (up to 9K) on both receive
and transmit
•
Hardware TCP/IP checksum on receive and
transmit
Three USB 2.0 ports
•
Each port can act as USB host or peripheral
•
USB 2.0 compliant
•
Integrated USB 2.0 PHY
•
EHCI compatible as a host
•
As a host, supports direct connection to all
peripheral types (LS, FS, HS)
•
As a peripheral, connects to all host types (HS, FS)
and hubs
•
Up to six independent endpoints supporting control,
interrupt, bulk, and isochronous data transfers
•
Dedicated DMA for data movement between
memory and port
Integrates Two Marvell 3 Gbps SATA PHYs
•
Compliant with SATA II Phase 1 specifications
-
Supports SATA II Native Command Queuing
(NCQ), up to 128 outstanding commands per
port
-
First party DMA (FPDMA) full support
-
Backwards compatible with SATA I devices
Device Bus controller
•
32-bit multiplexed address/data bus
•
Supports different types of standard memory
devices such as Flash, ROM, and SRAM
•
Supports NAND Flash
•
Five chip selects with programmable timing
•
Optional external wait-state support
•
8-, 16-, or 32-bit width device support
•
Up to 128-byte burst per single device bus access
•
Support for boot ROMs
Two PCI Express interfaces (x4)
•
PCI Express Base 1.1 compliant
•
Integrated low-power SERDES PHY, based on
proven Marvell SERDES technology
•
Can be configured as an Endpoint or as Root
Complex
•
x1/x4 link width, 2.5 GHz signalling
•
Lane polarity reversal support
•
Maximum payload size of 128 bytes
•
Single Virtual Channel (VC-0)
•
Replay buffer support
•
Extended PCI Express configuration space
•
Advanced Error Reporting (AER) support
•
Power management: L0s and SW L1 support
•
Interrupt emulation message support
•
Error message support
Configurable PCI Express x4 or Quad x1 port
•
Each one of the PCI Express ports can be
configured to act as four independent x1 ports; this
is useful for interfacing multiple off-the-shelf
PCI-Express devices.
•
Each of the x1 ports is PCI Express Base 1.1
compliant, has its own register file, and supports
the full feature set as the x4 port.
PCI Express Master specific features
•
Host to PCI Express bridge—translates CPU
cycles to PCI Express Memory or configuration
cycles
•
Supports DMA bursts between memory and
PCI-Express
•
Supports up to four outstanding read transactions
•
Maximum read request of up to 128 bytes
•
Maximum write request of up to 128 bytes
•
Supports SATA II Phase 2 advanced features
-
3 Gbps SATA II speed
-
Port Multiplier (PM)—Performs FIS-Based
Switching as defined in SATA working group PM
definition
-
Port Selector (PS)—Issues the protocol-based
OOB sequence to select the active host port
•
Supports device 48-bit addressing
•
Supports ATA Tag Command Queuing
MV-S104552-U0 Rev. D
Page 4
Document Classification: Proprietary Information
Copyright © 2008 Marvell
December 6, 2008, Preliminary
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
