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MV78100-A0-BHO1C100 参数 Datasheet PDF下载

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型号: MV78100-A0-BHO1C100
PDF下载: 下载PDF文件 查看货源
内容描述: 发现™系列的创新CPU系列硬件规格 [Discovery™ Innovation Series CPU Family Hardware Specifications]
分类和应用:
文件页数/大小: 124 页 / 1524 K
品牌: MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
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MV78100  
Hardware Specifications  
Table 63: Revision History (Continued)  
Document Type  
Revision  
Date  
Section 7, System Power Up and Reset Settings  
Added Section 7.1, Power Up/Down Sequence Requirements, on page 49.  
Updated Note on page 52.  
Added new NF reset strap.  
Added DEV_ALE modes strap.  
Added more clocking operating points.  
Section 9, Electrical Specifications (Preliminary)  
Updated Section 9.3, Thermal Power Dissipation (Preliminary), on page 64.  
Updated Section 9.4, Current Consumption (Preliminary), on page 65.  
Section 9.6.1, Reference Clock and Reset AC Timing Specifications, on page 70  
Added parameters for an SPI output clock, integrated with the TDM interface.  
Section 9.6.6, SDRAM DDR2 Interface AC Timing  
Replaced 64-bit 333 MHz Interface Timing and Clock Specification tables with 64-bit 400 MHz tables.  
Added:  
Table 37, SDRAM DDR2 400 MHz Interface Address and Control Timing Table, on page 82  
Table 39, SDRAM DDR2 333 MHz Interface AC Timing Table, on page 84  
Table 41, SDRAM DDR2 333 MHz Clock Specifications, on page 86  
Table 40, SDRAM DDR2 333 MHz Interface Address and Control Timing Table, on page 85  
Table 42, SDRAM DDR2 266 MHz Interface AC Timing Table, on page 87  
Updated Figure 21, SDRAM DDR2 Interface Write AC Timing Diagram, on page 89.  
Updated Figure 23, SDRAM DDR2 Interface Read AC Timing Diagram, on page 90.  
Section 9.6.8, Two-Wire Serial Interface (TWSI) AC Timing  
Updated TWSI output waveform Figure 30, TWSI Output Delay AC Timing Diagram, on page 95.  
Section 9.6.10, JTAG Interface AC Timing, on page 100.  
Updated section.  
Section 9.6.11, Time Division Multiplexing (TDM) Interface AC Timing, on page 102.  
Added section.  
Section 9.7, Differential Interface Electrical Characteristics  
Updated Table 51, PCI Express Interface Differential Reference Clock Characteristics, on page 104 to reflect both  
input and output modes.  
Section 9.7.3, SATA Interface Electrical Characteristics  
In Table 54, SATA I Interface Gen1i Mode Driver and Receiver Characteristicss, on page 108, return loss  
parameters (TX and RX) were added according to updated standard.  
Section 10, Thermal Data (Preliminary), on page 116  
Updated section.  
Section 12, Part Order Numbering/Package Marking, on page 118  
Updated section.  
Initial Release  
A
October 9, 2007  
MV-S104552-U0 Rev. D  
Page 122  
Copyright © 2008 Marvell  
December 6, 2008, Preliminary  
Document Classification: Proprietary Information  
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