Revision History
Table 63: Revision History (Continued)
Document Type
Revision
Date
Section 9.7, Differential Interface Electrical Characteristics
•
Added note that the spread spectrum requirements are defined on a linear sweep or a Hershey’s kiss modulation
in Table 52, PCI Express Interface Spread Spectrum Requirements, on page 105.
Section 9.7.3, SATA Interface Electrical Characteristics
•
Added Table 55, SATA I Interface Gen1m Mode Driver and Receiver Characteristics, on page 109 and Table 57,
SATA II Interface Gen2m Mode Driver and Receiver Characteristics, on page 111.
Section 10, Thermal Data (Preliminary), on page 116.
Updated thermal data.
•
Section 11, Package Mechanical Dimensions, on page 117.
•
Updated Figure 45, “655 Pin FCBGA Package and Dimensions in Section 11, Package Mechanical Dimensions,
on page 117. The capacitors have been removed from the figure.
Release
B
June 2, 2008
Product Overview
•
•
•
•
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Suppports 40-bit/72-bit DDR2 SDRAM interface
Integrates four 16550-compatible UART ports; also supports DMA based transmit
Integrates a two-channel SLIC/Codec TDM interface
®
Feroceon core supports 32-Kbyte I-Cache and 32-Kbyte D-Cache, parity protected
PCI Express port is PCI Express Base 1.1 compliant
Section 2, Pin Information:
•
•
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Added thermal diode pins THERMAL_A/C and TCLK_IN note in TCLK_OUT pin
Added pullups on MPP pins
Added M_CLKOUT[2:0] and M_CLKOUTn[2:0] in Table 5, DDR SDRAM Interface Pin Assignments, on page 23
Revised Table 6, Device Bus Interface Pin Assignments, on page 26
Updated Table 7, p. 28 added Table 8, PCI Express Common Pin Assignments, on page 28
Changed SPI pins names
Updated TDM interface signals
Added power pins to Table 10, USB 2.0 Ports 0/1/2 Interface Pin Assignments, on page 33 and Table 15, TDM
Interface Pin Assignments, on page 36
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Changed TWSI1 from VDDO_B to VDDO_A in Table 12, TWSI Interface Pin Assignments, on page 34
Section 4, MV78100 Pin Map and Pin List
•
•
Pinout list and map are embedded as an attachment.
Updates are recorded in the pinout Revision History.
Section 5, Clocking
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Added TCLK:N feature
Updated Figure 3, MV78100 Clocks, on page 42
Section 6, Pin Multiplexing
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Updated Note on page 48.
Changed column 0x0 so that device does not wake up in default with multiple pins have same functionality (e.g.
multiple pins assigned as GPIO[0]).
Updated UART1 muxing.
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Removed UA1_TXD and UA1_RXD from multiplexing table.
Fixed GPIO muxing.
Updated locations of SYSRST_OUTn.
Removed SYSRST_OUTn from Dev_AD[15] and Dev_WEn[2], and put it on Dev_AD[21,24,29,30,31].
Copyright © 2008 Marvell
MV-S104552-U0 Rev. D
Page 121
December 6, 2008, Preliminary
Document Classification: Proprietary Information
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
