Electrical Specifications
9.6.6.5
SDRAM DDR2 266 MHz Interface AC Timing Table
Table 41: SDRAM DDR2 266 MHz Interface AC Timing Table
266 MHz @ 1.8V
Description
Symbol
Min
Max
Units Notes
Clock frequency
fCK
tDOVB
tDOVA
tDIPW
tDQSH
tDQSL
tDSS
266.0
MHz
ns
-
DQ and DM valid output time before DQS transition
DQ and DM valid output time after DQS transition
DQ and DM output pulse w idth
0.42
0.42
0.35
0.35
0.35
0.34
0.34
-0.11
0.35
0.41
0.45
0.45
-0.50
1.20
2.90
0.30
0.67
-
-
-
ns
-
-
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
-
DQS output high pulse w idth
-
-
DQS output low pulse w idth
-
-
DQS falling edge to CLK-CLKn rising edge
DQS falling edge from CLK-CLKn rising edge
CLK-CLKn rising edge to DQS output rising edge
DQS w rite preamble
-
1
tDSH
-
1
tDQSS
tWPRE
tWPST
tCH
0.11
-
-
-
DQS w rite postamble
-
-
CLK-CLKn high-level w idth
0.55
1
CLK-CLKn low -level w idth
tCL
0.55
1
DQ input setup time relative to DQS in transition
DQ input hold time relative to DQS in transition
Address and Control valid output time before CLK-CLkn rising edge
Address and Control valid output time after CLK-CLKn rising edge
Address and control output pulse w idth
tDSI
-
-
-
-
-
-
-
tDHI
ns
tAOVB
tAOVA
tIPW
ns
1, 2
1, 2
-
ns
tCK
Notes :
General comment: All timing values w ere measured from vref to vref, unless otherw ise specified.
General comment: All input timing values assume minimum slew rate of 1 V/ns (slew rate measured from Vref +/-125 mV).
General comment: tCK = 1/fCK.
General comment: For all signals, the load is CL = 16 pF.
1. This timing value is defined on CLK / CLKn crossing point.
2. This timing value is defined w hen Address and Control signals are output ¼tCK after CLK-CLKn rising edge.
For more information, see register settings.
Copyright © 2008 Marvell
MV-S105424-U0 Rev. B
Page 87
December 6, 2008, Preliminary
Document Classification: Proprietary Information
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
