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MV76100-A0-BHO-C060 参数 Datasheet PDF下载

MV76100-A0-BHO-C060图片预览
型号: MV76100-A0-BHO-C060
PDF下载: 下载PDF文件 查看货源
内容描述: 发现™系列的创新CPU系列硬件规格 [Discovery™ Innovation Series CPU Family Hardware Specifications]
分类和应用:
文件页数/大小: 118 页 / 1444 K
品牌: MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
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Electrical Specifications  
9.6.6  
SDRAM DDR2 Interface AC Timing  
9.6.6.1  
SDRAM DDR2 400 MHz Interface AC Timing Table  
Table 35: SDRAM DDR2 400 MHz Interface AC Timing Table  
400 MHz @ 1.8V  
Description  
Symbol  
Min  
Max  
Units  
MHz  
Notes  
Clock frequency  
fCK  
tDOVB  
tDOVA  
tDIPW  
tDQSH  
tDQSL  
tDSS  
tDSH  
tDQSS  
tWPRE  
tWPST  
tCH  
400.0  
-
-
DQ and DM valid output time before DQS transition  
DQ and DM valid output time after DQS transition  
DQ and DM output pulse w idth  
0.38  
0.38  
0.35  
0.35  
0.35  
0.34  
0.34  
-0.11  
0.35  
0.41  
0.48  
0.48  
-0.40  
0.60  
0.67  
-
ns  
-
ns  
-
-
tCK(avg)  
tCK(avg)  
tCK(avg)  
tCK(avg)  
tCK(avg)  
tCK(avg)  
tCK(avg)  
tCK(avg)  
-
DQS output high pulse w idth  
-
-
DQS output low pulse w idth  
-
-
DQS falling edge to CLK-CLKn rising edge  
DQS falling edge from CLK-CLKn rising edge  
CLK-CLKn rising edge to DQS output rising edge  
DQS w rite preamble  
-
1
1
-
-
0.11  
-
-
DQS w rite postamble  
-
-
CLK-CLKn high-level w idth  
0.52  
tCK(avg) 1, 2, 3  
tCK(avg) 1, 2, 4  
CLK-CLKn low -level w idth  
tCL  
0.52  
DQ input setup time relative to DQS in transition  
DQ input hold time relative to DQS in transition  
Address and control output pulse w idth  
tDSI  
-
-
-
ns  
ns  
-
-
-
tDHI  
tIPW  
tCK(avg)  
Notes :  
General comment: All timing values w ere measured from vref to vref, unless otherw ise specified.  
General comment: All input timing values assume minimum slew rate of 1 V/ns (slew rate measured from Vref +/-125 mV).  
General comment: All timing parameters w ith DQS signal are defined on DQS-DQSn crossing point.  
General comment: For Address and Control output timing parameters, refer to the Address Timing table.  
General comment: tCK = 1/fCK.  
General comment: For all signals, the load is CL = 14 pF.  
1. This timing value is defined on CLK / CLKn crossing point.  
2. Refer to SDRAM DDR2 clock specifications table for more information.  
3. tCH(avg) is defined as the average HIGH pulse w idth, as calculated across any consecutive 200 HIGH pulses.  
4. tCL(avg) is defined as the average LOW pulse w idth, as calculated across any consecutive 200 LOW pulses.  
Copyright © 2008 Marvell  
MV-S105424-U0 Rev. B  
Page 81  
December 6, 2008, Preliminary  
Document Classification: Proprietary Information