Electrical Specifications
9.6.2
Reduced Gigabit Media Independent Interface (RGMII) AC
Timing
9.6.2.1
RGMII AC Timing Table
Table 31: RGMII AC Timing Table
Description
Clock frequency
Symbol
fCK
Min
Max Units Notes
125.0
MHz
ns
-
2
Data to Clock output skew
Data to Clock input skew
Clock cycle duration
Tskew T
Tskew R
Tcyc
-0.50
1.00
7.20
0.45
0.40
0.50
2.60
8.80
0.55
0.60
ns
-
ns
1 , 2
2
Duty cycle for Gigabit
Duty_G
Duty_T
tCK
tCK
Duty cycle for 10/100 Megabit
2
Notes :
General comment: All values w ere measured from vddio/2 to vddio/2, unless otherw ise specified.
General comment: tCK = 1/fCK.
General comment: If the PHY does not support internal-delay mode, the PC board design requires
routing clocks so that an additional trace delay of greater than 1.5 ns and less
than 2.0 ns is added to the associated clock signal.
For 10/100 Mbps RGMII, the Max value is unspecified.
1. For RGMII at 10 Mbps and 100 Mbps, Tcyc w ill scale to 400 ns +/-40 ns and 40 ns +/-4 ns, respectively.
2. For all signals, the load is CL = 5 pF.
9.6.2.2
RGMII Test Circuit
Figure 8: RGMII Test Circuit
Test Point
CL
Copyright © 2008 Marvell
MV-S105424-U0 Rev. B
Page 73
December 6, 2008, Preliminary
Document Classification: Proprietary Information
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
