Product Overview
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Command queuing support, for up to 128
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outstanding commands
Separate SATA request/response queues
64-bit addressing support for descriptors and data
buffers in system memory
Read ahead
Advanced interrupt coalescing
Advanced drive diagnostics via the ATA SMART
command
Two XOR DMAs
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Useful for RAID application
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Supports XOR operation on up to eight source
blocks
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Supports also iSCSI CRC-32 calculation
Interrupt controller
Maskable interrupts to CPU core
(and PCI Express in the case of PCI Express
Endpoint)
Four General Purpose 32-bit Timer/Counters
SPI port
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General purpose SPI interface
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Also support boot from SPI ROM
Two TWSI interfaces
General purpose TWSI master/slave
24 Multi-Purpose pins dedicated for peripheral
functions and General Purpose I/O
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Each pin can be configured independently
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GPIO inputs can be used to register interrupts from
external devices, and to generate maskable
interrupts
Clock Generation
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Supports internal generation of CPU core clock,
DRAM clock, core clock, GbE clock, USB clock,
and SATA clock from a single 25 MHz reference
clock
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Also supports spread spectrum reference clock
Power Down support
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Supports CPU Wait for Interrupt mode (shut down
CPU core clock)
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Selectable gating of clock trees of different
interfaces
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Supports DRAM self-refresh
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Supports PCI-Express, USB, and SATA PHYs shut
down
27 x 27 mm FCBGA package, 1mm ball pitch
Cryptographic engine
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Hardware implementation on encryption and
authentication engines to boost packet processing
speed
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Dedicated DMA to feed the hardware engines with
data from the internal SRAM memory or from the
DDR memory
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Implements AES, DES, and 3DES encryption
algorithms
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Implements SHA1 and MD5 authentication
algorithms
Three UART interfaces
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16550 UART compatible
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Each port has two pins for transmit and receive
operations, and two pins for modem control
functions
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One channel also supports DMA
Four Channel Independent DMA controller
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Chaining via linked-lists of descriptors
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Moves data from any interface to any interface
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DMA trigger by software or external hardware
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Supports increment or hold on both Source and
Destination Address
Copyright © 2008 Marvell
December 6, 2008, Preliminary
Document Classification: Proprietary Information
MV-S105424-U0 Rev. B
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