Clocking
Clock Domains
5
Clocking
5.1
Clock Domains
The MV76100 device has multiple clock domains:
PCLK: Sheeva™ CPU clock—up to 800 MHz
HCLK: The Sheeva™ CPU bus (MbusL) clock. Also used as the DRAM interface clock—up to
400 MHz
TCLK: The MV76100 core clock, also used as the reference clock for the MV76100 device bus.
Runs at 166 MHz or 200 MHz.
PCI-Express clock: Runs at 250 MHz
GbE ports clock: 125 MHz for 1000 Mbps, 25 MHz for 100 Mbps, and 2.5 MHz for 10 Mbps
operation
SATA clock: Runs at 150 Mhz
USB clock: Runs at 480 MHz
UART clock. Up to TCLK frequency divided by 16
SPI clock: Up to 50 MHz
TWSI clock: Up to 100 kHz
The supported PCLK to HCLK clock ratios are 1, 1.5, 2, 2.5, 3, 3.5, and 4 determined via reset
strapping. Table 18 summarizes the possible frequencies.
Table 18: HCLK and PCLK Frequencies
HCLK/Ratio
1
1.5
NA
2
2.5
500
625
667
750
NA
3
3.5
700
NA
NA
NA
N/A
NA
4
4.5
NA
NA
NA
NA
NA
NA
5
200
250
267
300
333
400
NA
NA
NA
NA
NA
400
400
500
533
600
667
800
600
750
800
NA
NA
NA
800
NA
NA
NA
N/A
NA
NA
NA
NA
NA
NA
NA
NA
400
450
500
600
NA
5.2
PLLs and Clock Pins
The MV76100 has the following on-chip PLLs:
PCLK PLL—Generates PCLK (Sheeva™ core clock) and HCLK (Sheeva™ bus and SDRAM I/F
clock)
TCLK PLL—Generates the internal core frequency
GE_CLK125 PLL—Generates 125 MHz reference clock for the GbE MAC
PCI Express PHY PLL
Copyright © 2008 Marvell
December 6, 2008, Preliminary
MV-S105424-U0 Rev. B
Document Classification: Proprietary Information
Page 41
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
