MV76100
Hardware Specifications
13 Revision History
Table 61: Revision History
Document Type
Release
Revision
Date
B
December 6, 2008
Section 2, Pin Information:
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•
•
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Added the SYSRST_OUTn pin to Table 4, Miscellaneous Pin Assignments, on page 24. This signal is multiplexed
on the MPP pins.
Added the M_BB pin to Table 5, DDR SDRAM Interface Pin Assignments, on page 26. The SDRAM battery
backup signal trigger is multiplexed on the MPP pins.
Changed the value to from 5 kilohm to 4.99 kilohm for PEXn_ISET in Table 7, PCI Express Port 0/1 Interface Pin
Assignments, on page 30.
Added the SATA_PRESENTn and SATA_ACTn pins to Table 11, SATA II Port Interface Pin Assignments, on
page 35. These signals are multiplexed on the MPP pins.
Section 3, Unused Interface Strapping:
Updated pull up and pull down resistor values in Table 17, Unused Interface Strapping, on page 39.
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Section 7, System Power Up and Reset Settings, on page 49.
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•
Added power rail information to Table 21, Reset Configuration, on page 52.
Corrected the configuration settings for DEV_AD[30] (NAND Flash Initialization Command) in Table 21 .
Section 9.6.7, Serial Peripheral Interface (SPI) AC Timing
Added AC timing information for this interface.
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Section 9.6.9, Device Bus Interface AC Timing
•
Changed the minimum values for tAOAB from 5.0 ns to 7.5 ns and tAOAA from 5.0 ns to 3.5 ns in Table 46, Device
Bus Interface AC Timing Table (when using TCLK_OUT as the reference clock), on page 97.
Initial Release
A
July 7, 2008
MV-S105424-U0 Rev. B
Page 118
Copyright © 2008 Marvell
December 6, 2008, Preliminary
Document Classification: Proprietary Information
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
