Features
2
S/PDIF / I S Audio In/Out interface (88F6192 only)
Serial Peripheral Interface (SPI) controller
2
• Up to 41.6 MHz clock
• Either S/PDIF or I S inputs can be active at one
• Supports direct boot from external SPI serial flash
memory
time
2
• Both S/PDIF and I S outputs can be active
MPEG Transport Stream (TS) interface (88F6192
only)
simultaneously, transferring the same PCM data
S/PDIF-specific features (88F6192 only)
• Compliant with 60958-1, 60958-3, and IEC61937
specifications
• Sample rates of 44.1/48/96 kHz
• 16/20/24-bit depths
I2S-specific features (88F6192 only)
• ISO/IEC 13818-1 standard compliant
• Supports any one of the following modes:
- Parallel (8 bit) input
- Parallel output
- Two independent serial interfaces
• Data rate up to 80 Mbps
• Sample rates of 44.1/48/96 kHz
Two UART interfaces
2
2
• I S input and I S output operate at the same
sample rate
• 16550 UART compatible
• Two pins for transmit and receive operations
• Two pins for modem control functions
• 16/24-bit depths
2
2
• I S in and I S out support independent bit depths
Two-Wire Serial Interface (TWSI)
(16 bit/24 bit)
2
• General purpose TWSI master/slave port
• Can also be used for serial ROM initialization
• Supports plain I S, right-justified and left-justified
formats
36 dedicated Multi-Purpose Pins (MPPS) for
peripheral functions and general purpose I/O
• Each pin can be configured independently.
• GPIO inputs can be used to register interrupts from
external devices, and to generate maskable
interrupts.
SD/SDIO/MMC host interface
• 1-bit/4-bit SDmem, SDIO, and MMC cards
• Up to 50 MHz
• Hardware generate/check CRC, on all command
and data transactions on the card bus
TDM SLIC/SLAC Codec interface (88F6192 only)
• Generic interface to standard SLIC/SLAC codec
devices
• In the 88F6192, one of the following multiplexed
interfaces may be configured at a time:
- Audio
- TS
- TDM
• Compatible with standard PCM highway formats
• TDM protocol support for two channels, up to
128 time slots
• Dedicated SPI interface for codec management
• Integrated DMA to transfer voice data to/from
memory buffer
- GbE Port 0 in GMII mode or GbE Port 1
Interrupt Controller
Maskable interrupts to CPU core
(and PCI Express for a PCI Express endpoint)
Two XOR engines and DMA
Two general purpose 32-bit timers/counters
Internal architecture
• Two XOR/DMA channels per XOR engine (for a
total of four XOR/DMA channels)
• Chaining via linked-lists of descriptors
• Moves data from source interface to destination
interface
• Mbus-L bus for high-performance, low-latency CPU
core to DDR SDRAM connectivity
• Advanced Mbus architecture
• Dual port DDR SDRAM controller connectivity to
both CPU and Mbus
• Supports increment or hold on both Source and
Destination Addresses
Bootable from
• SPI flash
• Supports XOR operation, on up to eight source
blocks—useful for RAID applications
• Supports iSCSI CRC-32 calculation
• SATA device
• NAND flash
• PCI Express
• UART (for debug purpose)
NAND flash controller
• 8-bit NAND flash interface
• Glueless interface to CE Care and CE Don’t Care
NAND flash devices
216-pin LQFP package, 24 x 24 mm, 0.4 mm pitch
• Boot support
Copyright © 2008 Marvell
Doc. No. MV-S104987-U0 Rev. F
December 2, 2008, Preliminary
Document Classification: Proprietary Information
Page 7
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
