88F6180
Hardware Specifications
30 Multi-Purpose Pins dedicated for peripheral
functions and general purpose I/O
•
Each pin can be configured independently.
•
GPIO inputs can be used to register interrupts from
external devices, and to generate maskable
interrupts.
Interrupt Controller
Maskable interrupts to CPU core
(and PCI Express for a PCI Express endpoint)
Two general purpose 32-bit timers/counters
Internal architecture
•
Mbus-L bus for high-performance, low-latency CPU
core to DDR SDRAM connectivity
•
Advanced Mbus architecture
•
Dual port DDR SDRAM controller connectivity to
both CPU and Mbus
Bootable from
•
SPI flash
•
NAND flash
•
PCI Express
•
UART (for debug purpose)
225-pin LFBGA package, 13 ×13 mm, 0.8 mm pitch
PCI Express
Mini Card Wi-Fi
GbE PHY
x1
SD Card
x16
On Board DDR2
88F6180
USB Host
Audio
A/D – D/A
x8
NAND Flash
SPI Flash
Usage Model Example: Access Point
Doc. No. MV-S104988-U0 Rev. E
Page 6
Document Classification: Proprietary Information
Copyright © 2008 Marvell
December 2, 2008, Preliminary
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
