88EM8040/88EM8041
Datasheet
Table 2: Pin Descriptions
Pin #
Pin Name
Pin Function
1
PGND
Power Ground
Connected to the source of the primary MOSFET. The PCB trace from the power ground to the
source of the primary MOSFET must be kept as short as possible.
To avoid any switching noise interruption on signal processing, PGND and SGND remain
seperate inside the IC.
2
3
4
SGND
ISNS
VIN
Signal Ground
Must be connected to the power ground with the Kelvin sensing connection, so that SGND has
dedicated trace and connections and provides noiseless environment for the signal processing.
Current Sense
Sense resistor varies from 0.15Ω at 120W rated load to 0.44Ω for 40W rated load. Used for
current shaping and for over current protection.
Voltage Input
•
Connects to resistive divider at input AC line “phase” to GND. Voltage applied is a half
rectified sine wave scaled down by the input resistive divider.
•
Voltage input pin is a high impedance input pin. An impedance of 2M (typical) is
recommended to be designed from the input AC “phase” to GND in order to reduce the
standby power. Higher impedance is preferred with the right PCB design on this pin signal.
•
•
Voltage is compared with a threshold reference (V
) to detect the zero-cross location
VIN_BR
of the input sine wave and synthesize (regenerate) the input sine wave. This sine wave is
used to generate the current reference.
1
Brown-out protection function is also provided by this pin. A resistor devider with a 100:1
ratio from the highside resistor to the lowside resistor is corresponding to the “brown-out
protection” input voltage as 50V (RMS). Increasing that raio will increase the “brown-out
1
voltage”. Please refer to footnote for further explaination.
5
FB
Feedback
It is connected to the emitter of the transistor on the secondary side of the opto coupler
(referred to within the Appication Information section). The output voltage is scaled to 2.5V with
100% rated value. Transition from soft start to normal regulation at 87.5% rated V . Over
FB
voltage shutdown SW gate signal at 107% rated V and recover once below V
.
FB
FB_OVP
There is another threshold (V
) as 3.77V on the FB pin. When FB Voltage reaches
FB_OVP_LATCH
V
, SW signal is shutdown and latched until another VDD power on reset.
FB_OVP_LATCH
6
7
OCP
VDD
Over Current Protection
Used to turn off the MOSFET when it is pulled as logic low
IC Supply Voltage
Nominal voltage is typical 12V and the Under Voltage Lock Out (UVLO) for V <V
DD
DD_UVLO
(Table 5). Start voltage of IC is V
(Table 5) and maximum voltage is 16V (Table 5). It
DD_On
should be clamped by a zener for protection in the system design.
8
SW
Switch
PWM gate signal for the switch. Connects to the gate of external MOSFET. It is the DSP core
output for ON/OFF time buffered through the internal adaptive driver.
1. Brown-out voltage is determined by Ra, Rb and Rc as shown in Figure 1. Please refer to page 29 for a further
understanding.
Doc. No. MV-S104983-01 Rev. A
Page 12
Copyright © 2009 Marvell
October 5, 2009, Preliminary
Document Classification: Proprietary
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
