List of Figures
List of Figures
Figure 1:
PFC Flyback Circuit Diagram ............................................................................................................3
1
Signal Description ........................................................................................................................... 11
Figure 2: SOIC-8 Pin Diagram (Top View).......................................................................................................11
2
3
Electrical Specifications ................................................................................................................. 13
Functional Description.................................................................................................................... 19
Figure 3:
Top Level Block Diagram..................................................................................................................19
4
Functional Characteristics.............................................................................................................. 21
Figure 4:
IDD Quiescent (IDD_QST) vs. VDD ...................................................................................................21
IDD vs. VDD (VDD_ON)........................................................................................................................21
Figure 5a:
Figure 5b: IDD vs. VDD (VDD_ON)........................................................................................................................21
Figure 6a:
Figure 6b:
Figure 7:
Figure 8:
Figure 9:
I
I
DD Operation (IDD_OP) vs. Temperature........................................................................................22
DD Operation (IDD_OP) vs. Temperature........................................................................................22
VDD On/Off vs. Temperature ...........................................................................................................22
DD vs. VFB (OVP).............................................................................................................................23
VFB_OVP vs. Temperature..............................................................................................................23
I
Figure 10: VFB_OVP Hysteresis vs. Temperature ............................................................................................23
Figure 11: VFB_OVP_LATCH vs. Temperature ................................................................................................23
Figure 12: Normal Regulation Reference (VFB_REG) vs. Temperature ...........................................................24
Figure 13: Switching Frequency vs. Temperature .............................................................................................24
Figure 14: Over Current (VIOVER) vs. Input Voltage VIN Peak Value).............................................................25
Figure 15: Over Current (VIOVER) vs. Temperature.........................................................................................25
Figure 16: VIOVER_CYC_ON/OFF vs. Temperature........................................................................................26
5
Design and Applications Information............................................................................................ 27
Figure 17: Internal Block for Zero-cross Detection, Brown-out Protection.........................................................28
Figure 18: Peak Detecting Signal for Predictive Sinusoidal AC Voltage............................................................29
Figure 19: Input Voltage Resistor Divider Layout Guidelines ............................................................................30
Figure 20: Secondary Compensation Network with Opt-coupler .......................................................................30
Figure 21: Bode Plot of Compensation Network at Secondary Side .................................................................32
Figure 22: Bias Current for Offset Voltage on FB Pin........................................................................................33
Figure 23: Current Sensing Circuit.....................................................................................................................34
Figure 24: Current Sensing and Cycle by Cycle Over Current Protection Circuit..............................................36
Figure 25: Current Sensing and Cycle by Cycle Over Current Protection Waveforms......................................36
Figure 26: SW Pin Layout Guidelines................................................................................................................39
Figure 27: VDD Decoupling Capacitor and Ground Layout Guidelines .............................................................40
Figure 28: 90W/20V Single Stage PFC Adaptor Schematic..............................................................................41
Copyright © 2009 Marvell
Doc. No. MV-S104983-01 Rev. A
Page 7
October 5, 2009, Preliminary
Document Classification: Proprietary
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
