Table of Contents
Table of Contents
SECTION 1. SIGNAL DESCRIPTION ........................................................................... 14
1.1 88E6060 128-Pin PQFP Package .............................................................................................14
1.2 Pin Description..........................................................................................................................15
SECTION 2. APPLICATION EXAMPLES....................................................................... 34
2.1 Examples with the 88E6060 .....................................................................................................34
2.2 Routing with the Marvell® Header...........................................................................................38
SECTION 3. FUNCTIONAL DESCRIPTION.................................................................... 39
3.1 Switch Data Flow ......................................................................................................................39
3.2 MII/SNI/RMII ...............................................................................................................................41
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
MII PHY Mode...........................................................................................................................41
MII MAC Mode ..........................................................................................................................42
SNI PHY Mode..........................................................................................................................43
RMII PHY Mode ........................................................................................................................44
RMII/MII/SNI Configuration .......................................................................................................45
Enabling the RMII/MII/SNI Interfaces........................................................................................45
Port Status Registers ................................................................................................................45
3.3 Media Access Controllers (MAC) ............................................................................................46
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
Backoff ......................................................................................................................................46
Half-Duplex Flow Control ..........................................................................................................46
Full-Duplex Flow Control...........................................................................................................47
Forcing Flow Control .................................................................................................................48
Statistics Counters ....................................................................................................................48
3.4 Address Management...............................................................................................................49
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
Address Translation Unit...........................................................................................................49
Address Searching or Translation.............................................................................................50
Address Learning ......................................................................................................................51
Address Aging...........................................................................................................................51
Address Translation Unit Operations ........................................................................................52
3.5 Ingress Policy............................................................................................................................56
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
Port-based VLANs.....................................................................................................................57
Switching Frames Back to their Source Port.............................................................................59
Port States.................................................................................................................................59
Switch’s Ingress Header (Port 4 and Port 5 only) .....................................................................59
Switch’s Ingress Trailer (Port 4 and Port 5 only).......................................................................60
3.6 Queue Controller.......................................................................................................................62
3.6.1 No Head-of-Line Blocking .........................................................................................................62
Copyright © 2008 Marvell
Doc. No. MV-S100952-U0 Rev. --
Page 5
January 3, 2008, Preliminary
Document Classification: Proprietary Information
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
