Table of Contents
Table of Contents
Product Overview.......................................................................................................................................3
1
Signal Description.......................................................................................................................21
Signal Diagram................................................................................................................................................21
128-Pin TQFP Package ..................................................................................................................................22
Pin Description................................................................................................................................................23
1.1
1.2
1.3
2
Functional Description................................................................................................................29
2.1
System Overview ............................................................................................................................................29
2.1.1
System Component Description .......................................................................................................29
2.1.1.1 Power Supplies ..................................................................................................................29
2.1.1.2 External Reference Clock...................................................................................................30
2.1.1.3 External TWSI EEPROM (VPD).........................................................................................30
2.2
Functional Overview........................................................................................................................................30
2.2.1
PCI Bus Interface Unit ......................................................................................................................30
2.2.1.1 Slave Access to Configuration Space ................................................................................31
2.2.1.2 Slave Access to Memory Resources..................................................................................31
2.2.1.3 Master Access....................................................................................................................31
2.2.1.4 Parity Generation/Check ....................................................................................................32
NAND Flash Controller .....................................................................................................................33
2.2.2.1 Write Operations ................................................................................................................33
2.2.2.2 Read Operations ................................................................................................................33
SDIO Host Controller........................................................................................................................38
2.2.3.1 Features .............................................................................................................................39
2.2.3.2 SD Bus Protocol Description..............................................................................................39
2.2.3.3 Special Bus Transactions...................................................................................................40
2.2.3.4 Card Detection ...................................................................................................................44
CMOS Camera Interface Controller..................................................................................................45
2.2.4.1 Features .............................................................................................................................45
2.2.4.2 I/O Signals..........................................................................................................................45
2.2.4.3 Interface Modes..................................................................................................................46
2.2.4.4 Input/Output Matrix.............................................................................................................47
2.2.4.5 Video Timing Reference Codes (SAV and EAV)................................................................47
2.2.4.6 RGB Input Data Formats....................................................................................................48
2.2.4.7 CCIC Recommended Programming Sequence .................................................................49
VPD Serial EEPROM........................................................................................................................49
2.2.5.1 VPD Serial EEPROM Loader.............................................................................................50
2.2.5.2 VPD Two-Wire Serial Interface ..........................................................................................51
Device Reset ....................................................................................................................................52
Reset Configuration..........................................................................................................................52
Clock Generation/Distribution...........................................................................................................52
PME on Wake up event....................................................................................................................52
2.2.9.1 Power Management Support..............................................................................................53
2.2.9.2 PCI Device Power States...................................................................................................53
2.2.9.3 Wake-Up Sequence ...........................................................................................................53
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
2.2.9
2.2.10 Clock Run (CLK_RUNn)...................................................................................................................54
2.2.11 Power on Reset Delay......................................................................................................................54
Copyright © 2007 Marvell
July 17, 2007, Preliminary
Doc. No. MV-S103921-00 Rev. –
Page 5
Document Classification: Proprietary Information
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
