®
LY61L2568
Rev. 0.4
256K X 8 BIT HIGH SPEED CMOS SRAM
DATA RETENTION CHARACTERISTICS
PARAMETER
SYMBOL TEST CONDITION
V
CC
for Data Retention
V
DR
CE#
≧
V
CC
- 0.2V
V
CC
= 2.0V
Normal
Data Retention Current
I
DR
CE#
≧
V
CC
- 0.2V
Others at 0.2V or V
CC
- 0.2V 20/25LL
See Data Retention
Chip Disable to Data
t
CDR
Waveforms (below)
Retention Time
Recovery Time
t
R
t
RC
*
= Read Cycle Time
MIN.
2.0
-
-
0
t
RC
*
TYP.
-
0.5
5
-
-
MAX.
3.6
1
40
-
-
UNIT
V
mA
µA
ns
ns
DATA RETENTION WAVEFORM
V
DR
≧
2.0V
Vcc
Vcc(min.)
t
CDR
CE#
V
IH
CE#
≧
Vcc-0.2V
Vcc(min.)
t
R
V
IH
Lyontek Inc.
reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
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