®
LY61L1024
Rev. 2.2
128K X 8 BIT HIGH SPEED CMOS SRAM
PIN DESCRIPTION
SYMBOL
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Inputs
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
FUNCTIONAL BLOCK DIAGRAM
Vcc
Vss
A0 - A16
DQ0 – DQ7
DECODER
128Kx8
MEMORY ARRAY
CE#, CE2
WE#
OE#
V
CC
V
SS
NC
A0-A16
DQ0-DQ7
I/O DATA
CIRCUIT
COLUMN I/O
CE#
CE2
WE#
OE#
CONTROL
CIRCUIT
PIN CONFIGURATION
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SOJ
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
CE2
WE#
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
A11
A9
A8
A13
WE#
CE2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
DQ0
A0
A1
A2
A3
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
Lyontek Inc.
reserves the rights to change the specifications and products without notice.
LY61L1024
LY61L1024
TSOP-I/STSOP
2
LYONTEK [ Lyontek Inc. ]
