®
LY61L256
32K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.4
DATA RETENTION CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITION
MIN.
TYP. MAX. UNIT
VCC for Data Retention
VDR CE# ≧ VCC - 0.2V
CC = 2.0V
2.0
-
3.6
V
V
Normal
LL
-
-
0.3
2
mA
CE# ≧ VCC - 0.2V
Data Retention Current
IDR
VCC = 2.0V
CE# ≧ VCC - 0.2V
Others at 0.2V or VCC-0.2V
0.5
20
A
µ
Chip Disable to Data
Retention Time
Recovery Time
See Data Retention
Waveforms (below)
tCDR
tR
0
-
-
-
-
ns
ns
tRC
*
tRC = Read Cycle Time
*
DATA RETENTION WAVEFORM
VDR ≧ 2.0V
Vcc(min.)
Vcc
Vcc(min.)
tCDR
tR
VIH
CE# ≧ Vcc-0.2V
VIH
CE#
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
7
LYONTEK [ Lyontek Inc. ]
