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LY61L102516AML-10 参数 Datasheet PDF下载

LY61L102516AML-10图片预览
型号: LY61L102516AML-10
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 1MX16, 10ns, CMOS, PDSO54, TSOP2-54]
分类和应用: 静态存储器光电二极管内存集成电路
文件页数/大小: 17 页 / 980 K
品牌: LYONTEK [ Lyontek Inc. ]
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LY61L102516A  
1024K X 16 BIT HIGH SPEED CMOS SRAM  
Rev. 1.3  
AC ELECTRICAL CHARACTERISTICS (VCC=2.7V~3.6V)  
(1) READ CYCLE  
LY61L102516A-10  
LY61L102516A-12  
PARAMETER  
SYM.  
UNIT  
MIN.  
MAX.  
MIN.  
MAX.  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Read Cycle Time  
tRC  
tAA  
10  
-
-
-
10  
10  
4.5  
-
12  
-
-
-
12  
12  
5
-
Address Access Time  
Chip Enable Access Time  
tACE  
tOE  
tCLZ  
tOLZ  
tCHZ  
tOHZ  
tOH  
tBA  
Output Enable Access Time  
Chip Enable to Output in Low-Z  
Output Enable to Output in Low-Z  
Chip Disable to Output in High-Z  
Output Disable to Output in High-Z  
Output Hold from Address Change  
LB#, UB# Access Time  
-
-
*
*
2
0
-
-
2
-
3
0
-
-
2
-
-
-
*
*
4
4
-
4.5  
4
5
5
-
5
5
-
LB#, UB# to High-Z Output  
LB#, UB# to Low-Z Output  
tBHZ  
tBLZ  
*
-
-
*
0
-
0
(2) WRITE CYCLE  
PARAMETER  
LY61L102516A-10  
LY61L102516A-12  
SYM.  
tWC  
tAW  
tCW  
tAS  
UNIT  
MIN.  
10  
8
MAX.  
MIN.  
12  
10  
10  
0
MAX.  
Write Cycle Time  
-
-
-
-
-
-
-
-
-
4
-
-
-
-
-
-
-
-
-
-
5
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Valid to End of Write  
Chip Enable to End of Write  
Address Set-up Time  
8
0
8
0
6
0
2
-
Write Pulse Width  
tWP  
tWR  
tDW  
tDH  
tOW  
10  
0
7
Write Recovery Time  
Data to Write Time Overlap  
Data Hold from End of Write Time  
Output Active from End of Write  
Write to Output in High-Z  
LB#, UB# Valid to End of Write  
0
2
-
*
tWHZ  
tBW  
*
8
10  
*These parameters are guaranteed by device characterization, but not production tested.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No.17, lndustry E . Rd.II, Science-Based Industrial Park, Hsinchu 300, Taiwan  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
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