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LY61L1024LL-12 参数 Datasheet PDF下载

LY61L1024LL-12图片预览
型号: LY61L1024LL-12
PDF下载: 下载PDF文件 查看货源
内容描述: [128K X 8 BIT HIGH SPEED CMOS SRAM]
分类和应用: 静态存储器
文件页数/大小: 17 页 / 512 K
品牌: LYONTEK [ Lyontek Inc. ]
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®
LY61L1024  
128K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 2.7  
AC ELECTRICAL CHARACTERISTICS  
(1) READ CYCLE  
PARAMETER  
SYM. LY61L1024-10 LY61L1024-12 LY61L1024-15 LY61L1024-18 UNIT  
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.  
Read Cycle Time  
Address Access Time  
Chip Enable Access Time  
Output Enable Access Time  
Chip Enable to Output in Low-Z  
Output Enable to Output in Low-Z tOLZ  
Chip Disable to Output in High-Z tCHZ  
Output Disable to Output in High-Z tOHZ  
Output Hold from Address Change tOH  
tRC  
tAA  
tACE  
tOE  
tCLZ  
10  
-
-
-
10  
10  
5
-
-
5
5
-
12  
-
-
-
12  
12  
6
-
-
6
6
-
15  
-
-
-
15  
15  
7
-
-
7
7
-
18  
-
-
-
18  
18  
8
-
-
8
8
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
-
-
-
-
*
*
*
*
2
0
-
-
3
3
0
-
-
3
4
0
-
-
3
4
0
-
-
3
(2) WRITE CYCLE  
PARAMETER  
SYM. LY61L1024-10 LY61L1024-12 LY61L1024-15 LY61L1024-18 UNIT  
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.  
Write Cycle Time  
tWC  
tAW  
tCW  
tAS  
tWP  
tWR  
tDW  
10  
8
8
0
8
0
6
0
2
-
-
-
-
-
-
-
-
-
-
6
12  
10  
10  
0
9
0
7
0
3
-
-
-
-
-
-
-
-
-
-
7
15  
12  
12  
0
10  
0
8
0
4
-
-
-
-
-
-
-
-
-
-
8
18  
16  
16  
0
11  
0
9
0
5
-
-
-
-
-
-
-
-
-
-
9
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Valid to End of Write  
Chip Enable to End of Write  
Address Set-up Time  
Write Pulse Width  
Write Recovery Time  
Data to Write Time Overlap  
Data Hold from End of Write Time tDH  
Output Active from End of Write  
Write to Output in High-Z  
tOW  
tWHZ  
*
*
*These parameters are guaranteed by device characterization, but not production tested.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
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