®
LY61L1024
128K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 2.7
DATA RETENTION CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITION
CE# ≧ VCC - 0.2V
or CE2 ≦ 0.2V
MIN.
TYP. MAX. UNIT
VCC for Data Retention
VDR
2.0
-
3.6
V
VCC = 2.0V
CE# ≧ VCC - 0.2V
or CE2 ≦ 0.2V
VCC = 2.0V
CE# ≧ VCC - 0.2V
or CE2 ≦ 0.2V
Normal
LL
-
0.006
2
mA
Data Retention Current
IDR
-
0.5
30
A
µ
others at 0.2V or VCC-0.2V
See Data Retention
Waveforms (below)
Chip Disable to Data
Retention Time
Recovery Time
tCDR
tR
0
-
-
-
-
ns
ns
tRC
*
tRC = Read Cycle Time
*
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) (CE# controlled)
VDR ≧ 2.0V
Vcc(min.)
Vcc
Vcc(min.)
tCDR
tR
VIH
CE# ≧ Vcc-0.2V
VIH
CE#
Low Vcc Data Retention Waveform (2) (CE2 controlled)
VDR ≧ 2.0V
Vcc(min.)
Vcc
Vcc(min.)
tCDR
tR
CE2 ≦ 0.2V
CE2
VIL
VIL
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
9
LYONTEK [ Lyontek Inc. ]
