®
LY61L10248A
1M X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.3
REVISION HISTORY
Revision
Description
Initial Issued
Issue Date
2012/2/21
Rev. 1.0
Rev. 1.1
July.19. 2012
≧
≦
1.“CE# VCC - 0.2V” revised as ”CE# 0.2” for TEST
CONDITION of Average Operating Power supply Current
Icc1 on page3
2.Revised ORDERING INFORMATION Page11
1.Revise “TEST CONDITION” for VOH, VOL on page 4
Rev. 1.2
Rev. 1.3
June. 04. 2013
IOH = -8mA revised as -4mA
IOL =4mA revised as 8mA
2.Revise VIH(max) & VIL(min) note on page 4
VIH(max) = VCC + 2.0V for pulse width less than 6ns.
VIL(min) = VSS - 2.0V for pulse width less than 6ns.
Revised the address pin sequence of TSOP-II pin configuration on
page 3 in order to be compatible with industry convention. (No
function specifications and applications have been changed and all
the characteristics are kept all the same as Rev 1.2 )
Oct. 30. 2013
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, lndustry E . Rd. 9, Science-Based Industrial Park, Hsinchu County 300, Taiwan
TEL: 886-3-6668838
FAX: 886-3-6668836
0
LYONTEK [ Lyontek Inc. ]
