®
LY61L10248A
1M X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.3
DATA RETENTION CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
VCC for Data Retention
VDR CE# ≧ VCC - 0.2V
CC =1.5V
1.5
-
3.6
V
V
-
-
Data Retention Current
IDR
3
25
mA
CE# ≧VCC - 0.2V;
Other pin is at 0.2V or Vcc-0.2V
Chip Disable to Data
Retention Time
Recovery Time
See Data Retention
Waveforms (below)
tCDR
tR
0
-
-
-
-
ns
ns
tRC
*
tRC = Read Cycle Time
*
DATA RETENTION WAVEFORM
VDR ≧ 1.5V
Vcc(min.)
Vcc
Vcc(min.)
tCDR
tR
VIH
CE# ≧ Vcc-0.2V
VIH
CE#
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, lndustry E . Rd. 9, Science-Based Industrial Park, Hsinchu County 300, Taiwan
TEL: 886-3-6668838
FAX: 886-3-6668836
8
LYONTEK [ Lyontek Inc. ]
