®
LY61L10248A
1M X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.3
CAPACITANCE (TA = 25℃, f = 1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
MIN.
-
-
MAX
8
10
UNIT
pF
pF
CIN
CI/O
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
speed
8ns/10/12ns
0.2V to Vcc-0.2V
3ns
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels 1.5V
CL = 30pF + 1TTL,
IOH/IOL = -4mA/8mA
Output Load
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
LY61L10248A
-8
LY61L10248A
-10
LY61L10248A
-12
PARAMETER
SYM.
UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
tRC
tAA
8
-
-
-
8
8
4.5
-
10
-
-
-
10
10
4.5
-
-
4
4
-
12
-
-
-
12
12
5
-
-
5
5
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
tACE
tOE
tCLZ
tOLZ
tCHZ
tOHZ
tOH
-
-
-
*
*
*
*
2
0
-
-
2
2
0
-
-
2
3
0
-
-
2
-
3
3
-
(2) WRITE CYCLE
PARAMETER
LY61L10248A
-8
MIN. MAX. MIN. MAX. MIN. MAX.
LY61L10248A
-10
LY61L10248A
-12
SYM.
UNIT
Write Cycle Time
tWC
tAW
tCW
tAS
tWP
tWR
tDW
8
6.5
6.5
0
6.5
0
-
-
-
-
-
-
10
8
8
0
8
-
-
-
-
-
-
12
10
10
0
10
0
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
0
Data to Write Time Overlap
5
-
6
-
7
-
ns
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High-Z
tDH
tOW
tWHZ
0
2
-
-
-
3
0
2
-
-
-
4
0
2
-
-
-
5
ns
ns
ns
*
*
*These parameters are guaranteed by device characterization, but not production tested.
TIMING WAVEFORMS
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, lndustry E . Rd. 9, Science-Based Industrial Park, Hsinchu County 300, Taiwan
TEL: 886-3-6668838
FAX: 886-3-6668836
5
LYONTEK [ Lyontek Inc. ]
