®
LY61L102416A
1024K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.4
Write Recovery Time
tWR
tDW
tDH
tOW
0
6
0
2
-
-
-
-
-
4
0
7
0
2
-
-
-
-
-
5
-
ns
ns
ns
ns
ns
ns
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High-Z
*
*
tWHZ
tBW
LB#, UB# Valid to End of Write
8
-
10
*These parameters are guaranteed by device characterization, but not production tested.
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
tRC
Address
tAA
tOH
Dout
Previous Data Valid
Data Valid
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)
tRC
Address
tAA
CE#
tACE
LB#,UB#
tBA
OE#
tOE
tOH
tOHZ
tBHZ
tCHZ
tOLZ
tBLZ
tCLZ
High-Z
Dout
High-Z
Data Valid
Notes :
1.WE#is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low, LB# or UB# = low.
3.Address must be valid prior to or coincident with CE# = low, LB# or UB# = low transition; otherwise tAA is the limiting parameter.
4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, lndustry E . Rd. 9, Science-Based Industrial Park, Hsinchu 300, Taiwan
TEL: 886-3-6668838
FAX: 886-3-6668836
5
LYONTEK [ Lyontek Inc. ]
