®
LY61L102416A
Rev. 1.2
1024K X 16 BIT HIGH SPEED CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled) (1,2)
t
RC
Address
t
AA
Dout
Previous Data Valid
t
OH
Data Valid
READ CYCLE 2
(CE# and OE# Controlled) (1,3,4,5)
t
RC
Address
t
AA
CE#
t
ACE
LB#,UB#
t
BA
OE#
t
OE
t
OLZ
t
BLZ
t
CLZ
Dout
High-Z
t
OH
t
OHZ
t
BHZ
t
CHZ
Data Valid
High-Z
Notes :
1.WE#is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low, LB# or UB# = low
.
3.Address must be valid prior to or coincident with CE# = low, LB# or UB# = low transition; otherwise t
AA
is the limiting parameter.
4.t
CLZ
, t
BLZ,
t
OLZ
, t
CHZ,
t
BHZ
and t
OHZ
are specified with C
L
= 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, t
CHZ
is less than t
CLZ
, t
BHZ
is less than t
BLZ
, t
OHZ
is less than t
OLZ.
Lyontek Inc.
reserves the rights to change the specifications and products without notice.
5F, No. 2, lndustry E . Rd. 9, Science-Based Industrial Park, Hsinchu 300, Taiwan
TEL: 886-3-6668838
FAX: 886-3-6668836
7
LYONTEK [ Lyontek Inc. ]
