®
LY6125616
Rev. 2.1
WRITE CYCLE 3
(
LB#,UB#
Controlled)
(1,2,5,6)
t
WC
Address
t
AW
CE#
t
AS
LB#,UB#
t
WP
WE#
t
WHZ
Dout
(4)
High-Z
t
DW
Din
t
DH
t
CW
t
BW
t
WR
5V 256K X 16 BIT HIGH SPEED CMOS SRAM
Data Valid
Notes :
1.WE#,CE#, LB#, UB# must be high during all address transitions.
2.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low.
3.During a WE# controlled write cycle with OE# low, t
WP
must be greater than t
WHZ
+ t
DW
to allow the drivers to turn off and data to be
placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance
state.
6.t
OW
and t
WHZ
are specified with C
L
= 5pF. Transition is measured ±500mV from steady state.
Lyontek Inc.
reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
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