®
LY6125616
5V 256K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 2.4
WRITE CYCLE 3 (LB#,UB# Controlled)
(1,2,5,6)
tWC
Address
tAW
tWR
CE#
tAS
tCW
tBW
LB#,UB#
WE#
tWP
tWHZ
High-Z
Dout
(4)
tDW
tDH
Din
Data Valid
Notes :
1.WE#,CE#, LB#, UB# must be high during all address transitions.
2.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low.
3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed
on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
DATA RETENTION CHARACTERISTICS
PARAMETER
VCC for Data Retention
SYMBOL
TEST CONDITION
CE# ≧ VCC - 0.2V
CC = 2.0V
CE# ≧ VCC - 0.2V
other pins at 0.2V or VCC-0.2V
MIN. TYP. MAX. UNIT
VDR
2.0
-
-
5.5
10
2
V
mA
mA
10
-
-
-
V
Data Retention Current
IDR
15/20/25
15/20/25LL
0.05
10
50
A
µ
Chip Disable to Data
Retention Time
Recovery Time
See Data Retention
Waveforms (below)
tCDR
tR
0
-
-
-
-
ns
ns
tRC
*
tRC = Read Cycle Time
*
DATA RETENTION WAVEFORM
VDR ≧ 2.0V
Vcc(min.)
Vcc
Vcc(min.)
tCDR
tR
VIH
CE# ≧ Vcc-0.2V
VIH
CE#
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
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