;Sample routines for PIC18CXXX interface
/***********************************************************************************************************************/
;Initialize PIC18Cxxx portc in LS7366 compatible SPI
;Setup: master mode, SCK idle low, SDI/SDO datashift on high to low transition of SCK
;SS/ assertion/deassertion made with direct manipulation of RA5
;Initialize portc
CLRF
CLRF
PORTC
LATC
;Clear portc
;Clear data latches
MOVLW
MOVWF
BCF
BSF
CLRF
0x10
TRISC
TRISA, 5
PORTA, 5
SSPSTAT
;RC4 is input, RC3 & RC5 are outputs
;RC3=CLK, RC4=SDI, RC5=SDO
;RA5=output
;RA5=SS/=high
;SMP=0 => SDI data sampled at mid-data
BSF
MOVLW
SSPSTAT, CKE ;CKE=1 => data shifts on active to idle SCK transitions
0x21
;SPI mode initialization data
MOVWF
SSPCON
;Master mode, CLK/16, CKP=0 => CLK idles low
;data shifted on active to idle CLK edge
/***********************************************************************************************************************/
; WR_MDR0
BSF
BCF
PORTA, 5
PORTA, 5
0x88
SSPBUF
SSPSTAT, BF
LOOP1
;SS/=high
;SS/=low
MOVLW
MOVWF
LOOP1 BTFSS
BRA
;LS7366 WR_MDR0 command
;Transmit command byte
;Transmission complete with BF flag set?
;No, check again
MOVF
SSPBUF, W
0xA3
SSPBUF
SSPSTAT, BF
LOOP2
;Dummy read to clear BF flag.
;MDR0 data:fck/2, synchronous index. index=rcntr, x4
;Transmit data
;BF set?
;No, check again
MOVLW
MOVWF
LOOP2 BTFSS
BRA
BSF
PORTA, 5
;SS/=high
/***********************************************************************************************************************/
;RD_MDR0
BSF
BCF
PORTA, 5
PORTA, 5
0x48
SSPBUF
SSPSTAT, BF
LOOP1
;SS/=high
;SS/=low
;LS7366 RD_MDR0 command
;Transmit command byte
;BF flag set?
MOVLW
MOVWF
LOOP1 BTFSS
BRA
;No, check again
MOVWF
LOOP2 BTFSS
BRA
SSPBUF
SSPSTAT, BF
LOOP2
;Send dummy byte to generate clock & receive data
;BF flag set?
;No, check again
MOVF
MOVWF
BSF
SSPBUF, W
RXDATA
PORTA, 5
;Recieved data in WREG.
;Save received data in RAM
;SS/=high
7366R-041906-13
LSI [ LSI COMPUTER SYSTEMS ]
